Intel Corporation patent applications on April 17th, 2025
Patent Applications by Intel Corporation on April 17th, 2025
Intel Corporation: 42 patent applications
Intel Corporation has applied for patents in the areas of H01L23/498 (6), H01L23/00 (6), H01L23/538 (5), H01L23/528 (4), H01L23/522 (4) H01L23/15 (2), H01L23/528 (2), B25J9/1605 (1), H01L23/5226 (1), H01L23/5381 (1)
With keywords such as: based, apparatus, device, conductive, circuitry, layer, having, portion, methods, and processor in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Julio Zamora Esquivel of West Sacramento CA US for intel corporation, Alberto Jaimes Pita of Zapopan MX for intel corporation, David Gonzalez Aguirre of Hillsboro OR US for intel corporation, Javier Felip Leon of Hillsboro OR US for intel corporation, Rodrigo Aldana Lopez of Zapopan MX for intel corporation, Edgar Macias Garcia of Zapopan MX for intel corporation, David Gomez Gutierrez of Tlaquepaque MX for intel corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/1605
Abstract: techniques are disclosed to implement a mathematical framework to model a mechanical actuator such as robotic arm and compute the differential kinematics of an end effector represented by a circle in a three-dimensional space, described as a bi-vector of conformal geometric algebra. additionally, by using a circle to describe the grasping pose on the object, a differential kinematics-based control scheme is implemented to guide the actuator and minimize the error between the end effector circle and the target circle. the circle has 3 degrees of freedom for the center, two degrees for the orientation, and one more for the radius, which may be used to describe the end effector pose, with the differential kinematics-based control scheme law adjusting the position and the orientations simultaneously.
20250123657. HINGE AND CHASSIS FOR FLEXIBLE DISPLAY_simplified_abstract_(intel corporation)
Inventor(s): Denica N. Larsen of Portland OR US for intel corporation, Chunlin Bai of ChengDu CN for intel corporation, Prosenjit Ghosh of Portland OR US for intel corporation, Surya Pratap Mishra of Hillsboro OR US for intel corporation
IPC Code(s): G06F1/16
CPC Code(s): G06F1/1681
Abstract: particular embodiments described herein provide for an electronic device that can be configured to include a chassis, where the chassis includes a first chassis portion and a second chassis portion, a flexible display supported by the chassis, and a hinge. the hinge includes a first chassis attachment housing coupled to the first chassis portion, a first chassis portion lift arm coupled to the first chassis attachment housing, a first hinge pivot coupled to the first chassis portion lift arm, a second chassis attachment housing coupled to the second chassis portion, a second chassis portion lift arm coupled to the second chassis attachment housing, and a second hinge pivot coupled to the second chassis portion lift arm. the first chassis portion lift arm extends to increase a first distance between the first chassis attachment housing and the first hinge pivot and the second chassis portion lift arm extends to increase a second distance between the second chassis attachment housing and the second hinge pivot as the flexible display is bent.
Inventor(s): Deepak Samuel Kirubakaran of Hillsboro OR US for intel corporation, Ho Jeong An of Portland OR US for intel corporation, Nisha Aram of Hillsboro OR US for intel corporation, Sravya Atluri of Santa Clara CA US for intel corporation, Simonjit Dutta of Sammamish WA US for intel corporation, Darwin Guo of Santa Clara CA US for intel corporation, Linlin Hou of Portland OR US for intel corporation, Yishin Huang of Portland OR US for intel corporation, Ho Kyu Kang of Portland OR US for intel corporation, Brice Onken of Hillsboro OR US for intel corporation, Veeraraghavan Ramaraj of Hillsboro OR US for intel corporation, Cameron Rieck of Portland OR US for intel corporation, Malavika Srinivas of Hillsboro OR US for intel corporation, Venkateshan Udhayan of Portland OR US for intel corporation, Fidel Angel Vanegas Patino of Vancouver WA US for intel corporation, Zhongsheng Wang of Ridgefield WA US for intel corporation, Ulises Zaragoza of Santa Clara CA US for intel corporation
IPC Code(s): G06F1/3296
CPC Code(s): G06F1/3296
Abstract: a component of a computing system, including: processor circuitry; and a non-transitory computer-readable storage medium including instructions that, when executed by the processor circuitry, cause the processor circuitry to: dynamically monitor runtime metrics across processor cores of the computing system, wherein the runtime metrics comprise a measure of system-critical task residency and a measure of user-critical foreground application utilization; and initiate a power optimization action configured to transition the computing system into a power efficiency mode when the system-critical task residency is below a system-critical task residency threshold and the user-critical foreground application utilization is below a user-critical foreground application utilization threshold.
20250123749. DETECTION OF MEMORY ACCESSES_simplified_abstract_(intel corporation)
Inventor(s): Navneet SINGH of Bangalore IN for intel corporation, Hugh WILKINSON of Newton MA US for intel corporation, Sushant KUMAR of Bengaluru IN for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: examples described herein relate to hot page detection. some examples include circuitry to provide a number of pages with access counts within a bucket of a histogram, wherein the bucket of the histogram is associated with a configured access count range; based on a distribution of access counts in the histogram being a first level, reduce the configured access count ranges of the different buckets of the histogram; determine a second level indicative of page access counts; and migrate data of pages from a far memory to a near memory based on the second level.
Inventor(s): Jyotsna Khemka of Bangalore IN for intel corporation, Saurabh Tiwari of Bangalore IN for intel corporation
IPC Code(s): G06F8/35, G06N3/0895
CPC Code(s): G06F8/35
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to utilize large language artificial intelligence models to convert computer code. an example apparatus includes instructions and processor circuitry to execute the instructions to at least: train a large language model based on a computer instructions repository that includes code of a first type; utilize the large language model to convert an input set of instructions of the first type into output code of a second type; cause execution of the output code; determine if the execution is successful; and when the execution is not successful, utilize the output code for fine-tuning training of the large language model with incorrect data.
Inventor(s): Nitin N. Garegrat of San Jose CA US for intel corporation, Tony L. Werner of Los Altos CA US for intel corporation, Jeff DelChiaro of Scotts Valley CA US for intel corporation, Michael Rotzin of Santa Clara CA US for intel corporation, Robert T. Rhoades of San Jose CA US for intel corporation, Ujwal Basavaraj Sajjanar of San Jose CA US for intel corporation, Anne Q. Ye of Sunnyvale CA US for intel corporation
IPC Code(s): G06F9/345, G06F9/30, G06F17/16
CPC Code(s): G06F9/3455
Abstract: in one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. the matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.
20250123848. INTER-PROCESSOR COMMUNICATIONS_simplified_abstract_(intel corporation)
Inventor(s): Yi-Feng LIU of Chandler AZ US for intel corporation, Eric J. DEHAEMER of Shrewsbury MA US for intel corporation, Eswaramoorthi NALLUSAMY of Cedar Park TX US for intel corporation
IPC Code(s): G06F9/4401, G06F9/54
CPC Code(s): G06F9/4403
Abstract: examples described herein relate to partitioning of processor sockets. a first processor socket includes first communication circuitry associated with a first partition identifier and a second processor socket includes a second communication circuitry associated with a second partition identifier. in some examples, based on a boot operation associated with the first processor socket: the first communication circuitry is to permit communication with the second communication circuitry based on a first partition identifier matching the second partition identifier and the first communication circuitry is to disable communication with the second communication circuitry based on the first partition identifier not matching the second partition identifier.
Inventor(s): Rajesh M. SANKARAN of Portland OR US for intel corporation, Gilbert NEIGER of Hillsboro OR US for intel corporation, Narayan RANGANATHAN of Bangalore IN for intel corporation, Stephen R. VAN DOREN of Portland OR US for intel corporation, Joseph NUZMAN of Haifa IL for intel corporation, Niall D. MCDONNELL of Limerick IE for intel corporation, Michael A. O'HANLON of Limerick IE for intel corporation, Lokpraveen B. MOSUR of Gilbert AZ US for intel corporation, Tracy Garrett DRYSDALE of Paradise Valley AZ US for intel corporation, Eriko NURVITADHI of Hillsboro OR US for intel corporation, Asit K. MISHRA of Hillsboro OR US for intel corporation, Ganesh VENKATESH of Hillsboro OR US for intel corporation, Deborah T. MARR of Portland OR US for intel corporation, Nicholas P. CARTER of Somerville MA US for intel corporation, Jonathan D. PEARCE of Hillsboro OR US for intel corporation, Edward T. GROCHOWSKI of San Jose CA US for intel corporation, Richard J. GRECO of Hillsboro OR US for intel corporation, Robert VALENTINE of Kiryat Tivon IL for intel corporation, Jesus CORBAL of King City OR US for intel corporation, Thomas D. FLETCHER of Sherwood OR US for intel corporation, Dennis R. BRADFORD of Portland OR US for intel corporation, Dwight P. MANLEY of Holliston MA US for intel corporation, Mark J. CHARNEY of Lexington MA US for intel corporation, Jeffry J. COOK of Portland OR US for intel corporation, Paul CAPRIOLI of Hillsboro OR US for intel corporation, Koichi YAMADA of Los Gatos CA US for intel corporation, Kent D. GLOSSOP of Merrimack NH US for intel corporation, David B. SHEFFIELD of Hillsboro OR US for intel corporation
IPC Code(s): G06F9/48, G06F9/30, G06F9/38
CPC Code(s): G06F9/48
Abstract: embodiments of systems, methods, and apparatuses for heterogeneous computing are described. in some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
Inventor(s): Prabhakar Subrahmanyam of San Jose CA US for intel corporation, Mark Angus MacDonald of Beaverton OR US for intel corporation, Mainak Banga of Folsom CA US for intel corporation, Jeffrey Christopher Sedayao of San Jose CA US for intel corporation, Ying Feng Pang of San Jose CA US for intel corporation
IPC Code(s): G06F9/48, G06F1/20
CPC Code(s): G06F9/4893
Abstract: systems, apparatus, and methods for energy harvesting in data centers are disclosed. an example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to estimate first power consumption values for electronic components of a first rack; estimate second power consumption values for electronic components of a second rack; determine a first selection score for the first rack based on the first power consumption values and a second selection score for the second rack based on the second power consumption values; select a first electronic component of the first rack or a second electronic component of the second rack to receive a workload based on the first selection score and the second selection score; and cause the selected one of the first electronic component or the second electronic component to perform the workload.
Inventor(s): Zion S. KWOK of Burnaby CA for intel corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1044
Abstract: a memory subsystem performs error correction through erasure decoding instead of ecc (error correction code) polynomial computation. an error correction module of the memory controller receives a data word and calculates a syndrome using the data word. the error correction module generates multiple correctable error pattern candidates for bounded fault regions based on erasure decoding. the error correction module selects one correctable error pattern candidate to apply error correction.
20250123955. PROGRAMMABLE WRITE FILTER HARDWARE_simplified_abstract_(intel corporation)
Inventor(s): Frank T. Hady of Cannon Beach OR US for intel corporation, Scott D. Peterson of Beaverton OR US for intel corporation, Andrzej Stasiak of Borkowo PL for intel corporation
IPC Code(s): G06F12/02, G06F12/0815
CPC Code(s): G06F12/0223
Abstract: write filter hardware is provided with circuitry to receive a signal to switch the write filter from a disabled state to an enabled state for a given range of addresses in a shared memory. a write attempt by a host processor to the range of addresses is identified, where access to the shared memory is shared with an accelerator device. the write filter hardware causes the write attempt to be dropped when the hardware write filter is in the enabled state for the given range of addresses.
Inventor(s): Aruni P. Nelson of Rocklin CA US for intel corporation, Rajesh Poornachandran of Portland OR US for intel corporation
IPC Code(s): G06F13/20
CPC Code(s): G06F13/20
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to dynamically manage input/output (i/o) transactions. an example apparatus includes circuitry to determine at least one of a first parameter assigned to an vo transaction by a user, a second parameter for the i/o transaction based on at least a class of an i/o device, or a third parameter for the i/o transaction based on a usage pattern for a compute device coupled to the i/o device. additionally, the example apparatus includes parameter management circuitry to determine a dynamic parameter to assign to the i/o transaction based on at least one of the first parameter, the second parameter, or the third parameter and cause scheduler circuitry to at least one of adjust a default bandwidth to be allocated to the i/o transaction based on the dynamic parameter or adjust a latency associated with the i/o transaction based on the dynamic parameter.
20250123988. ADJUSTMENT OF PORT CONNECTIVITY OF AN INTERFACE_simplified_abstract_(intel corporation)
Inventor(s): Liron ELMALEH of Beer Tuvia IL for intel corporation, Eliel LOUZOUN of Jerusalem IL for intel corporation, Yosef Hai AMAR of Ashdod IL for intel corporation, Alon MEIR of Jerusalem IL for intel corporation
IPC Code(s): G06F13/42, G06F13/40
CPC Code(s): G06F13/4221
Abstract: examples described herein relate to a network interface device. the network interface device includes a host interface; a network interface; and a direct memory access (dma) circuitry. in some examples, the host interface includes circuitry to: apply a first configuration of peripheral component interconnect express (pcie) upstream ports and downstream ports and without reboot of the network interface device, apply a second configuration to adjust routing of communication among devices coupled to the pcie upstream ports and downstream ports.
Inventor(s): Gopi Krishna Jha of Mysore IN for intel corporation, Sameh Gobriel of Dublin CA US for intel corporation, Nilesh Jain of Portland OR US for intel corporation
IPC Code(s): G06F17/16
CPC Code(s): G06F17/16
Abstract: key-value (kv) caching accelerates inference in large language models (llms) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. due to large context lengths in modern llms, kv cache size can exceed the model size, which can negatively impact throughput. to address this issue, kvcrush, which stands for key-value cache size reduction using similarity in head-behavior, is implemented. kvcrush involves using binary vectors to represent tokens, where the vector indicates which attention heads attend to the token and which attention heads disregard the token. the binary vectors are used in a hardware-efficient, low-overhead process to produce representatives for unimportant tokens to be pruned, without having to implement k-means clustering techniques.
Inventor(s): Przemyslaw Maziewski of 80298 Gdansk Pomeranian PL for intel corporation, Lukasz Pindor of Pruszcz Gdanski, Pomorskie, 83-000 PL for intel corporation, Adam Kupryjanow of Gdansk PL for intel corporation
IPC Code(s): G06F21/62, G10L15/02, G10L21/007, G10L25/30, H04L9/40
CPC Code(s): G06F21/6254
Abstract: voice anonymization systems and methods are provided. voice anonymization is done on the speaker's computing device and can prevent voice theft. the voice anonymization systems and methods are lightweight and run efficiently in real time on a computing device, allowing for speaker anonymity without diminishing system performance during a teleconference or voip meeting. the anonymization system outputs a transformed speaker voice. the anonymization system can also generate a voice embedding that can be used to reconstruct the original speaker voice. the voice embedding can be encrypted and transmitted to another device. sometimes, the voice embedding is not transmitted and the listener receives the anonymized voice. systems and methods are provided for the detection of voice transformations in received audio. thus, a listener can be informed whether the speaker voice output from the listener's computing device is the original speaker's voice or a transformed version of the original speaker voice.
Inventor(s): Kamlesh Pillai of Bangalore IN for intel corporation, Gurpreet S. Kalsi of Bangalore IN for intel corporation, Amit Mishra of Bangalore IN for intel corporation
IPC Code(s): G06N3/048, G06F7/499, G06F7/556, G06F17/11, G06F17/17, G06N3/044, G06N3/045, G06N3/063, G06N3/084
CPC Code(s): G06N3/048
Abstract: in one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (pla) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of pla equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.
Inventor(s): Estelle Aflalo of Haifa IL for intel corporation, Amit Bleiweiss of Yad Binyamin IL for intel corporation, Mattias Marder of Haifa IL for intel corporation, Eliran Zimmerman of Maalot IL for intel corporation
IPC Code(s): G06N3/063, G06F9/50, G06F18/21, G06N3/08
CPC Code(s): G06N3/063
Abstract: methods, apparatus, systems and articles of manufacture are disclosed to map workloads. an example apparatus includes a constraint definer to define performance characteristic targets of the neural network, an action determiner to apply a first resource configuration to candidate resources corresponding to the neural network, a reward determiner to calculate a results metric based on (a) resource performance metrics and (b) the performance characteristic targets, and a layer map generator to generate a resource mapping file, the mapping file including respective resource assignments for respective corresponding layers of the neural network, the resource assignments selected based on the results metric.
20250124596. HEAD POSE ESTIMATION IN COMPUTER VISION_simplified_abstract_(intel corporation)
Inventor(s): Shahar Shmuel Yuval of Haifa IL for intel corporation, Maxim Khokhlov of Santa Clara CA US for intel corporation, Noam Levy of Karmiel IL for intel corporation
IPC Code(s): G06T7/73, G06V40/16
CPC Code(s): G06T7/73
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to estimate a pose of a head of a user of an electronic device. an example apparatus to estimate a head pose includes at least one processor circuit to be programmed by instructions to: identify a plurality of facial landmarks in a plurality of images; identify initial image data based on the plurality of facial landmarks; augment the initial image data with a transformation operation; and train a neural network based on the initial image data and the augmented image data to: infer three-dimensional model parameters; and infer a confidence metric.
Inventor(s): Hava Matichin of Petah Tikva IL for intel corporation, Dor Barber of Herzliya IL for intel corporation, Bin Yang of ShangHai CN for intel corporation, Qing You of Beijing CN for intel corporation
IPC Code(s): G06V10/25, G06T3/40, G06T5/92, G06V40/16, H04N9/73
CPC Code(s): G06V10/25
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for high quality and low power dynamic region of interest (roi) cropping. an example apparatus disclosed herein provides a first image to image signal processor (isp) circuitry, the isp circuitry to implement an image processing pipeline to process the first image. the example apparatus also downscales the first image to generate a second image having lower resolution than the first image and identifies a region of interest (roi) in the second image. the example apparatus further provides coordinates of the roi to the isp circuitry, the isp circuitry to crop the first image based on the coordinates and to output a third image based on the cropped first image.
Inventor(s): Adam Kupryjanow of Gdansk PL for intel corporation, Lukasz Pindor of Pruszcz Gdanski PL for intel corporation
IPC Code(s): G10L21/0208, G06N3/08, G10L21/0232, G10L25/30, G10L25/78, H04R3/04
CPC Code(s): G10L21/0208
Abstract: a method and system of neural network dynamic noise suppression (dns) is provided for audio processing. the system is a down-scaled dns model that uses grouping techniques at pointwise convolutional layers to reduce the number of network parameters. according to one technique, audio signal data can be coded into an input vector that that is split into multiple groups, each groups having multiple channels. at a pointwise convolution layer, an output is generated for each group. the outputs can be concatenated to form a single input vector for a next layer of the model. each group is treated as a channel, such that the reduction in the number of channels reduces the number of parameters used by the neural network. in some examples, the groups are weight sharing groups.
Inventor(s): Dat T. LE of Tigard OR US for intel corporation, George VERGIS of Portland OR US for intel corporation, Alejandro LARIOS of Zapopan MX for intel corporation
IPC Code(s): G11C29/02, G11C29/14, G11C29/44
CPC Code(s): G11C29/021
Abstract: methods and apparatus for ddr5 dimm power fail monitor to prevent i/o reverse-bias current. an apparatus is configured to be implemented in a host system including a processor having an integrated memory controller (imc) coupled to one or more dimms having an onboard power management integrated circuit (pmic). the apparatus includes circuitry to monitor an operating state for a host voltage regulator (vr) providing input power to the processor and monitor an operating state of the pmic for each of the one or more dimms. in response to detecting a fault condition of the host vr or a pmic for a dimm, the apparatus prevents reverse bias voltage in circuitry in at least one of the imc and the one or more dimms. the apparatus may implement a finite state machine (fsn) having a plurality of defined states including a fault state used to indicate detection of the fault condition.
Inventor(s): Brandon Christian Marin of Gilbert AZ US for intel corporation, Whitney Bryks of Tempe AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Jason Gamba of Gilbert AZ US for intel corporation, Haifa Hariri of Phoenix AZ US for intel corporation, Sashi Shekhar Kandanur of Phoenix AZ US for intel corporation, Joseph Peoples of Gilbert AZ US for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ US for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Joshua James Stacey of Chandler AZ US for intel corporation, Hiroki Tanaka of Gilbert AZ US for intel corporation, Jacob Ryan Vehonsky of Chandler AZ US for intel corporation
IPC Code(s): H01L23/15, H01L23/18, H01L23/498, H01L23/64
CPC Code(s): H01L23/15
Abstract: package substrates with components included in cavities of glass cores are disclosed. an example apparatus includes: a glass core having a first through-hole and a second through-hole, the first through-hole spaced apart from and smaller than the second through-hole; and a conductive material within the first through-hole, the conductive material to extend a full length of the first through-hole. the example apparatus further includes a dielectric material within the second through-hole, the dielectric material between an electronic component within the second through-hole and a sidewall of the second through-hole.
Inventor(s): Brandon Christian Marin of Gilbert AZ US for intel corporation, Whitney Bryks of Tempe AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Jason Gamba of Gilbert AZ US for intel corporation, Haifa Hariri of Phoenix AZ US for intel corporation, Sashi Shekhar Kandanur of Phoenix AZ US for intel corporation, Joseph Peoples of Gilbert AZ US for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ US for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Joshua James Stacey of Chandler AZ US for intel corporation, Hiroki Tanaka of Gilbert AZ US for intel corporation, Jacob Ryan Vehonsky of Chandler AZ US for intel corporation
IPC Code(s): H01L23/15, H01L23/18, H01L23/498, H01L23/64
CPC Code(s): H01L23/15
Abstract: package substrates with components included in cavities of glass cores are disclosed. an example apparatus includes: a glass layer having an opening between opposing first and second surfaces of the glass layer; an electronic component within the opening; a dielectric material within the opening between the electronic component and a sidewall of the opening; and a through-glass via including a conductive material that extends through the glass layer.
20250125242. VIA PLUG RESISTOR_simplified_abstract_(intel corporation)
Inventor(s): Santosh Gangal of Bangalore IN for intel corporation, Tin Poay Chuah of Bayan Baru MY for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H05K1/11, H05K1/16, H05K3/42, H10D1/47, H10D1/68
CPC Code(s): H01L23/49827
Abstract: disclosed herein are via plug resistors for incorporation into electronic substrates, and related methods and devices. exemplary via plug resistor structures include a resistive element within and on a surface of a via extending at least partially through an electronic substrate and first and second electrodes coupled to the resistive element.
Inventor(s): Andy Chih-Hung Wei of Yamhill OR US for intel corporation, Guillaume Bouche of Portland OR US for intel corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/528
CPC Code(s): H01L23/5226
Abstract: disclosed herein are methods for fabricating ic structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting ic structures. an example ic structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. the ic structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). the bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. the bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (sam) material.
20250125259. INTERNAL NODE JUMPER FOR MEMORY BIT CELLS_simplified_abstract_(intel corporation)
Inventor(s): Smita SHRIDHARAN of Beaverton OR US for intel corporation, Zheng GUO of Portland OR US for intel corporation, Eric A. KARL of Portland OR US for intel corporation, George SHCHUPAK of Zviya IL for intel corporation, Tali KOSINOVSKY of Haifa IL for intel corporation
IPC Code(s): H01L23/528, H01L23/535, H10B10/00, H10D84/85
CPC Code(s): H01L23/528
Abstract: memory bit cells having internal node jumpers are described. in an example, an integrated circuit structure includes a memory bit cell on a substrate. the memory bit cell includes first and second gate lines parallel along a second direction of the substrate. the first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. first, second and third interconnect lines are over the first and second gate lines. the first, second and third interconnect lines are parallel along the second direction of the substrate. the first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. one of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
20250125260. ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Richard E. SCHENKER of Portland OR US for intel corporation, Robert L. BRISTOL of Portland OR US for intel corporation, Kevin L. LIN of Beaverton OR US for intel corporation, Florian GSTREIN of Portland OR US for intel corporation, James M. BLACKWELL of Portland OR US for intel corporation, Marie KRYSAK of Portland OR US for intel corporation, Manish CHANDHOK of Beaverton OR US for intel corporation, Paul A. NYHUS of Portland OR US for intel corporation, Charles H. WALLACE of Portland OR US for intel corporation, Curtis W. WARD of Hillsboro OR US for intel corporation, Swaminathan SIVAKUMAR of Beaverton OR US for intel corporation, Elliot N. TAN of Portland OR US for intel corporation
IPC Code(s): H01L23/528, H01L23/522, H01L23/532, H10D30/69, H10D84/83
CPC Code(s): H01L23/528
Abstract: advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. self-assembled devices and their methods of fabrication are described.
Inventor(s): Jianyong XIE of Chandler AZ US for intel corporation, Sujit SHARAN of Chandler AZ US for intel corporation, Huang-Ta CHEN of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/498, H01L23/64, H01L25/18
CPC Code(s): H01L23/5381
Abstract: embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. in an embodiment, a bridge comprises a substrate and a routing stack over the substrate. in an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.
Inventor(s): Aleksandar ALEKSOV of Chandler AZ US for intel corporation, Adel A. ELSHERBINI of Chandler AZ US for intel corporation, Kristof DARMAWIKARTA of Chandler AZ US for intel corporation, Robert A. MAY of Chandler AZ US for intel corporation, Sri Ranga Sai BOYAPATI of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/31, H01L23/498, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L23/5386
Abstract: an apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. other embodiments are also disclosed and claimed.
Inventor(s): Srinivas V. PIETAMBARAM of Gilbert AZ US for intel corporation, Sri Ranga Sai BOYAPATI of Chandler AZ US for intel corporation, Robert A. MAY of Chandler AZ US for intel corporation, Kristof DARMAWIKARTA of Chandler AZ US for intel corporation, Javier SOTO GONZALEZ of Chandler AZ US for intel corporation, Kwangmo LIM of Chandler AZ US for intel corporation
IPC Code(s): H01L23/538, H01L23/00
CPC Code(s): H01L23/5389
Abstract: a foundation layer and methods of forming a conductive via are described. a die pad is formed over a die. a seed layer is deposited over the die pad and the foundation layer. a first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. a conductive material is deposited into the conductive line opening to form a conductive line. a second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. the conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. the second and first layers are removed. portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
Inventor(s): Jeremy Ecton of Gilbert AZ US for intel corporation, Jason M. Gamba of Gilbert AZ US for intel corporation, Brandon C. Marin of Gilbert AZ US for intel corporation, Srinivas V. Pietambaram of Chandler AZ US for intel corporation, Xiaoxuan Sun of Phoenix AZ US for intel corporation, Omkar G. Karhade of Chandler AZ US for intel corporation, Xavier Francois Brun of Hillsboro OR US for intel corporation, Yonggang Li of Chandler AZ US for intel corporation, Suddhasattwa Nad of Chandler AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Haobo Chen of Chandler AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/538
CPC Code(s): H01L25/0652
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (rdl) on the first layer, wherein the rdl includes conductive vias having a greater width towards a first surface of the rdl and a smaller width towards an opposing second surface of the rdl; wherein the first surface of the rdl is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the rdl, wherein the second die is electrically coupled to the rdl by second solder interconnects having a second solder, wherein the second solder is different than the first solder.
Inventor(s): Laurent CARIOU of Milizac FR for intel corporation, Thomas J. KENNEY of Portland OR US for intel corporation
IPC Code(s): H04B7/0417, H04W24/02, H04W74/0816
CPC Code(s): H04B7/0417
Abstract: this disclosure describes systems, methods, and devices related to nav timeout. a device may transmit, during a transmission opportunity (txop), an initial control frame (icf) trigger frame including user information fields identifying one or more target stations (stas). the device may receive from the one or more target stas, an initial control response (icr) frame, wherein the icr frame includes feedback information and padding. the device may calculate a network allocation vector (nav) timeout period based on a transmission time of a maximum-sized icr frame at a lowest transmission rate. the device may adjust nav settings based on the nav timeout period.
20250125896. NETWORK-BASED TIME SYNCHRONIZATION_simplified_abstract_(intel corporation)
Inventor(s): David R. MULVIHILL of Fort Collins CO US for intel corporation, Srinivasan S. IYENGAR of Fremont CA US for intel corporation, Mark BORDOGNA of Andover MA US for intel corporation, Subrahmanya Kumar KUCHIBHOTLA of Bangalore IN for intel corporation
IPC Code(s): H04J3/06, H04W56/00
CPC Code(s): H04J3/0658
Abstract: examples described herein relate to a timing source. in some examples, the timing source generates a clock signal by synchronization with a second clock signal from a crystal source and subsequent synchronization with a third clock signal. in some examples, the third clock signal is synchronized to timing signals received in ethernet packets. in some examples, the crystal source is to provide the second clock signal to the circuitry via the interface.
20250125944. SECURING AUDIO COMMUNICATIONS_simplified_abstract_(intel corporation)
Inventor(s): Pradeep M. Pappachan of Tualatin OR US for intel corporation, Reshma Lal of Portland OR US for intel corporation, Rakesh A. Ughreja of Bangalore IN for intel corporation, Kumar N. Dwarakanath of Folsom CA US for intel corporation, Victoria C. Moore of Phoenix AZ US for intel corporation
IPC Code(s): H04L9/00, G06F9/54, G06F21/44, G06F21/57, G06F21/60, G06F21/83, G06F21/84, H04L9/08, H04L9/40
CPC Code(s): H04L9/00
Abstract: systems and methods include establishing a cryptographically secure communication between an application module and an audio module. the application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. the establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.
20250125966. INTEGRITY PROTECTED COMMAND BUFFER EXECUTION_simplified_abstract_(intel corporation)
Inventor(s): Pradeep M. Pappachan of Tualatin OR US for intel corporation, Reshma Lal of Portland OR US for intel corporation
IPC Code(s): H04L9/32, G06F21/60, H04L9/08
CPC Code(s): H04L9/3226
Abstract: embodiments are directed to providing integrity-protected command buffer execution. an embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.
Inventor(s): Wey-Yi Guy of Beaverton OR US for intel corporation, Tao Tao of Portland OR US for intel corporation, Venkateshan Udhayan of Portland OR US for intel corporation, Sean J. W. Lawrence of Bangalore IN for intel corporation, Perazhi Sameer Kalathil of Bangalore IN for intel corporation, Vishal Ravindra Sinha of Portland OR US for intel corporation
IPC Code(s): H04L12/18, G06F1/3209
CPC Code(s): H04L12/1822
Abstract: systems, apparatus, articles of manufacture, and methods to save power during conference calls are disclosed. an example first client device includes interface circuitry; machine readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine readable instructions to: determine whether a first attendee of a conference call is absent from the first client device; and cause transmission of a notification to at least one of a server for the conference call or a second client device associated with the conference call and different from the first client device, the notification to cause the second client device to change an operating state associates with the conference call.
Inventor(s): Kartik LAKHOTIA of San Jose CA US for intel corporation, Hossein FARROKHBAKHT of Toronto CA for intel corporation, Gurpreet Singh KALSI of Portland OR US for intel corporation, Fabrizio PETRINI of Menlo Park CA US for intel corporation
IPC Code(s): H04L45/02, H04L45/00
CPC Code(s): H04L45/02
Abstract: examples described herein relate to performing source routing of a packet to route the packet from a source to a destination through multiple routers by specification of a path of logical port identifiers through the multiple routers. in some examples, multiple routers are to translate the logical port identifiers into physical ports based on configurations. in some examples, the path of the packet through the multiple routers is based on a topology of the routers.
20250126189. PACKET LOAD BALANCER_simplified_abstract_(intel corporation)
Inventor(s): Ping YU of Shanghai CN for intel corporation, Hongjun NI of Shanghai CN for intel corporation, Tao ZHU of Chengdu CN for intel corporation, Houxiang CAI of Chengdu CN for intel corporation, Wenjian SHAO of Shanghai CN for intel corporation
IPC Code(s): H04L69/22, H04L67/1004
CPC Code(s): H04L69/22
Abstract: examples described herein relate to processing packets. in some examples, based on receipt of a hypertext transfer protocol (http) packet at a network interface device, the http packet comprising an http body and http header: provide the http header, but not the http body, for processing in user space; modify solely the http header in user space; and in kernel space, combine the modified http header and the http body prior to transmission of the http packet with modified http header to a client.
Inventor(s): James Holland of Folsom CA US for intel corporation, Sang-hee Lee of San Jose CA US for intel corporation, Ximin Zhang of San Jose CA US for intel corporation, Zhan Lou of Shanghai CN for intel corporation
IPC Code(s): H04N19/126, G06N20/00, H04N19/149, H04N19/172
CPC Code(s): H04N19/126
Abstract: techniques related to adaptive quantization matrix selection using machine learning for video coding are discussed. such techniques include applying a machine learning model to generate an estimated quantization parameter for a frame and selecting a set of quantization matrices for encode of the frame from a number of sets of quantization matrices based on the estimated quantization parameter.
Inventor(s): Brandon Christian Marin of Gilbert AZ US for intel corporation, Whitney Bryks of Tempe AZ US for intel corporation, Gang Duan of Chandler AZ US for intel corporation, Jeremy Ecton of Gilbert AZ US for intel corporation, Jason Gamba of Gilbert AZ US for intel corporation, Haifa Hariri of Phoenix AZ US for intel corporation, Sashi Shekhar Kandanur of Phoenix AZ US for intel corporation, Joseph Peoples of Gilbert AZ US for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ US for intel corporation, Mohammad Mamunur Rahman of Gilbert AZ US for intel corporation, Bohan Shan of Chandler AZ US for intel corporation, Joshua James Stacey of Chandler AZ US for intel corporation, Hiroki Tanaka of Gilbert AZ US for intel corporation, Jacob Ryan Vehonsky of Chandler AZ US for intel corporation
IPC Code(s): H10D1/20, H01L23/15, H01L23/498, H01L23/538, H01L25/18
CPC Code(s): H10D1/20
Abstract: package substrates with components included in cavities of glass cores are disclosed. an example apparatus includes: a glass layer having a first hole and a second hole, the second hole larger than an electronic component disposed therein, a width of the electronic component larger than a width of the first hole. the example apparatus further includes a conductive material that substantially fills the first hole; and a dielectric material that substantially fills a space within the second hole surrounding the electronic component.
Inventor(s): Biswajeet GUHA of Hillsboro OR US for intel corporation, William HSU of Portland OR US for intel corporation, Leonard P. GULER of Hillsboro OR US for intel corporation, Dax M. CRUM of Beaverton OR US for intel corporation, Tahir GHANI of Portland OR US for intel corporation
IPC Code(s): H10D30/62, H01L21/02, H01L23/522, H10D30/67, H10D62/10, H10D62/13, H10D84/01, H10D84/03
CPC Code(s): H10D30/6217
Abstract: self-aligned gate endcap (sage) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (sage) architectures with gate-all-around devices, are described. in an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. a nanowire is over the semiconductor fin. a gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. a pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
Inventor(s): Subhash JOSHI of Hillsboro OR US for intel corporation, Michael J. JACKSON of Portland OR US for intel corporation, Michael L. HATTENDORF of Portland OR US for intel corporation
IPC Code(s): H10D64/01, H01L21/02, H01L21/033, H01L21/28, H01L21/285, H01L21/308, H01L21/311, H01L21/762, H01L21/768, H01L23/00, H01L23/522, H01L23/528, H01L23/532, H10B10/00, H10D1/47, H10D30/01, H10D30/62, H10D30/69, H10D62/00, H10D62/10, H10D62/13, H10D62/822, H10D62/834, H10D64/23, H10D64/68, H10D84/01, H10D84/03, H10D84/83, H10D84/85, H10D89/10
CPC Code(s): H10D64/017
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. a gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. a first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. a second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.
- Intel Corporation
- B25J9/16
- CPC B25J9/1605
- Intel corporation
- G06F1/16
- CPC G06F1/1681
- G06F1/3296
- CPC G06F1/3296
- G06F3/06
- CPC G06F3/0611
- G06F8/35
- G06N3/0895
- CPC G06F8/35
- G06F9/345
- G06F9/30
- G06F17/16
- CPC G06F9/3455
- G06F9/4401
- G06F9/54
- CPC G06F9/4403
- G06F9/48
- G06F9/38
- CPC G06F9/48
- G06F1/20
- CPC G06F9/4893
- G06F11/10
- CPC G06F11/1044
- G06F12/02
- G06F12/0815
- CPC G06F12/0223
- G06F13/20
- CPC G06F13/20
- G06F13/42
- G06F13/40
- CPC G06F13/4221
- CPC G06F17/16
- G06F21/62
- G10L15/02
- G10L21/007
- G10L25/30
- H04L9/40
- CPC G06F21/6254
- G06N3/048
- G06F7/499
- G06F7/556
- G06F17/11
- G06F17/17
- G06N3/044
- G06N3/045
- G06N3/063
- G06N3/084
- CPC G06N3/048
- G06F9/50
- G06F18/21
- G06N3/08
- CPC G06N3/063
- G06T7/73
- G06V40/16
- CPC G06T7/73
- G06V10/25
- G06T3/40
- G06T5/92
- H04N9/73
- CPC G06V10/25
- G10L21/0208
- G10L21/0232
- G10L25/78
- H04R3/04
- CPC G10L21/0208
- G11C29/02
- G11C29/14
- G11C29/44
- CPC G11C29/021
- H01L23/15
- H01L23/18
- H01L23/498
- H01L23/64
- CPC H01L23/15
- H01L21/48
- H01L23/00
- H05K1/11
- H05K1/16
- H05K3/42
- H10D1/47
- H10D1/68
- CPC H01L23/49827
- H01L23/522
- H01L21/768
- H01L23/528
- CPC H01L23/5226
- H01L23/535
- H10B10/00
- H10D84/85
- CPC H01L23/528
- H01L23/532
- H10D30/69
- H10D84/83
- H01L23/538
- H01L25/18
- CPC H01L23/5381
- H01L21/56
- H01L23/31
- H01L25/00
- H01L25/065
- CPC H01L23/5386
- CPC H01L23/5389
- CPC H01L25/0652
- H04B7/0417
- H04W24/02
- H04W74/0816
- CPC H04B7/0417
- H04J3/06
- H04W56/00
- CPC H04J3/0658
- H04L9/00
- G06F21/44
- G06F21/57
- G06F21/60
- G06F21/83
- G06F21/84
- H04L9/08
- CPC H04L9/00
- H04L9/32
- CPC H04L9/3226
- H04L12/18
- G06F1/3209
- CPC H04L12/1822
- H04L45/02
- H04L45/00
- CPC H04L45/02
- H04L69/22
- H04L67/1004
- CPC H04L69/22
- H04N19/126
- G06N20/00
- H04N19/149
- H04N19/172
- CPC H04N19/126
- H10D1/20
- CPC H10D1/20
- H10D30/62
- H01L21/02
- H10D30/67
- H10D62/10
- H10D62/13
- H10D84/01
- H10D84/03
- CPC H10D30/6217
- H10D64/01
- H01L21/033
- H01L21/28
- H01L21/285
- H01L21/308
- H01L21/311
- H01L21/762
- H10D30/01
- H10D62/00
- H10D62/822
- H10D62/834
- H10D64/23
- H10D64/68
- H10D89/10
- CPC H10D64/017