Intel Corporation patent applications on 2025-07-03
Patent Applications by Intel Corporation on July 3rd, 2025
Intel Corporation: 157 patent applications
Intel Corporation has applied for patents in the areas of H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({ takes precedence; manufacture or treatment } ; mountings per se ; {materials }), 10), H10D30/6735 (No explanation available, 4), H01L23/4821 (consisting of lead-in layers inseparably applied to the semiconductor body {(electrodes )}, 3), H01L23/49811 ({Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads ( takes precedence)}, 3), G06F9/30014 ({with variable precision}, 2), H01L23/49866 ({characterised by the materials (materials of the substrates , of the lead-frames )}, 2), H01L23/5223 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application), 2), H01L21/76897 ({Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step (self-aligned silicidation on field effect transistors )}, 2), H01L23/5381 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({ takes precedence; manufacture or treatment } ; mountings per se ; {materials }), 2), H01L23/642 ({Capacitive arrangements (, , , take precedence; capacitive effects between wiring layers on the semiconductor body )}, 2)
With keywords such as: device, plurality, includes, each, memory, control, storage, respectively, storing, boxes in patent application abstracts.
Top Inventors:
- Cornelius BUERKLE of Karlsruhe DE (5 patents)
- Frederik PASCH of Karlsruhe DE (2 patents)
- Fabian OBORIL of Karlsruhe DE (5 patents)
- Qutub SYED SHA of Munich DE (2 patents)
- Leobardo Campos Macias of Guadalajara MX (2 patents)
Patent Applications by Intel Corporation
Abstract: a control device includes a memory device storing, for each storage box of a plurality of storage boxes, respectively associated first box information indicating which multiple objects are arranged in the storage box and in which arrangement the multiple objects are in the storage box; and a processor configured to: receive identification data representing an identification of a storage box; determine the first box information associated with the storage box using the identification data; receive sensor data representing an image of the multiple objects arranged in the storage box; determine, via object recognition using the sensor data, second box information indicating which objects are arranged in the storage box; generate control instructions for controlling the robotic device to pick up at least one object of the multiple objects based on the first box information associated with the storage box and the second box information.
20250214242. ROBOTIC DEVICE WORKSPACE MAPPING (Intel)
Abstract: system and techniques to map a workspace for a robotic device are described herein. the robotic device has a movable portion with a sensor that is used to capture readings from part of the workspace. these readings are used to map a portion of the workspace and then to plot a new position of the movable portion to get readings for another part of the workspace. as the technique iterates, the robotic device is able to safely and efficiently map the entirety of the workspace.
20250214248. TECHNOLOGIES GENERATIVE AI WAREHOUSE PICKING (Intel)
Abstract: technologies for generative ai for warehouse picking are disclosed. in an illustrative embodiment, a robot can partially or fully autonomously perform object picking in a warehouse. a description of an object to be picked can be sent to a compute device controlling the robot. the compute device can direct the robot to move to where the object is located. the robot can then take a picture that can be analyzed. a text description as well as the image is encoded and provided to a transformer. the transformer generates an output vector indicating, e.g., where an end effector should grab hold of an object. a goal generator can then determine a pose for the end effector based on the output latent vector. a planner can move the end effector to the determined pose. a new picture can be taken, and the cycle can repeat until the item is picked.
20250214619. MANAGEMENT TRUST METRICS AUTONOMOUS VEHICLE OPERATION (Intel)
Abstract: a system of a vehicle having access to a network, includes a communication controller to interface with at least one of: a mobile device, the vehicle, and sensors coupled to the vehicle; and a vehicle controller to perform a responsive operation at the vehicle; where the system is to: identify a target vehicle operating in proximity of the vehicle; determine a trust metric, the trust metric indicating a measurement of risk to operate the vehicle in the proximity of the target vehicle; and initiate the responsive operation at the vehicle, using the vehicle controller, based on the trust metric.
20250216187. TUNABLE CASCADED MACH-ZEHNDER INTERFEROMETER STRUCTURES (Intel)
Abstract: cascaded mach-zehnder interferometer (cmzi) structures comprising electrically resistive heaters provisioned across the stages so as to enable improved filter wavelength control. in embodiments, cmzi heater power supply control is made a linear function by scaling the number of heater elements between the stages in proportion with the magnitude of the arm differential (e.g., �l, �l) for the corresponding stage.
20250216222. SENSOR DATA VERIFICATION (Intel)
Abstract: system and techniques to verify sensor data are described herein. when sensor data is received, the sensor data is recorded into a data store and a trust score is generated for at least a portion of the sensor data. the trust score is based on several factors including a measure of agreement between the sensor data and other sensor data of a scene. the trust score may then be used to measure the veracity of claims supported by the sensor data.
20250216247. VEHICLE LOAD WEIGHT ESTIMATION BASED OPERATING PARAMETERS VEHICLE (Intel)
Abstract: disclosed herein are devices, methods, and systems for estimating a load weight of a vehicle without measuring the weight of the vehicle (e.g., without a weight sensor). the load weight estimation may obtain an engine torque and a velocity of a vehicle when it is in motion. the load weight estimation may then determine, based on the engine torque and the velocity, an estimate of a load weight on the vehicle. the load weight estimation may then generate an instruction based on the estimate of the load weight. the load weight estimation may also use other operating parameters of the vehicle, such as tire pressure, a pose, acceleration, geographic location, road geometry, ambient temperature, road conditions, engine temperature, etc. to determine the estimate of the load weight.
20250216441. CLOCKLESS CALIBRATION-LESS DIFFERENTIAL AGING MONITOR (Intel)
Abstract: an aging detection circuit includes a sensor circuit and a reference circuit. the sensor circuit runs constantly with the operation of the device to be monitored. the sensor circuit can generate a sensor count. the reference circuit is turned off unless enabled for measurement of the device to be monitored. the reference circuit can generate a reference count. the aging detection circuit can include circuitry to determine the aging of the device to be monitored based on a difference between the sensor counter and the reference counter.
Abstract: an integrated circuit (ic) package comprises a stack with first and second electronic devices respectively having a first array and a second array of rows and columns of pads bonded to each other. at least one testing structure comprises a first pattern of first pads of the first array, a second pattern of second pads of the second array, and at least four pad-pairs of one of the first pads adjacent to one of the second pads, wherein each pair has different pads than the other pairs. an aligned state of the first and second electronic devices exists wherein each pad-pair has a different offset length separating the first pad from the second pad, and wherein none of the first and second pads of the pairs are electrically connected.
20250216601. SILICON PHOTONIC INTEGRATED CIRCUITS LOCALIZED THICK BURIED INSULATOR (Intel)
Abstract: a silicon photonic (siph) integrated circuit on a substrate comprising a buried insulator layer of varying thickness between an optical waveguide and an underlying silicon layer. the insulator layer has a first thickness under a first length of the waveguide and a second, greater, thickness under a second length of the waveguide. buried insulator layer thickness may be thinner where an optical mode is to be more confined during operation of the siph ic, and buried insulator layer thickness may be greater within localized regions where optical mode is to expand during operation of the siph ic. accordingly, a transfer of optical energy to an underlying silicon layer of the substrate may be curtailed within one substrate region without impeding the transfer of thermal energy to the underlying silicon layer within another substrate region.
20250216624. Comb Laser Source Architectures Photonic integrated Circuits (Intel)
Abstract: scalable heterogeneous (hybrid) silicon photonic (siph) wavelength division multiplexing laser source architectures suitable as a fiber-coupled external photonic ic (pic) source for high-bandwidth communication between computing resources. hybrid-silicon laser sources may be arrayed over a silicon substrate into physically separate banks of lasers, each bank spanning a different range of consecutive wavelength channels and each bank including physically separated odd and even channel groups within a channel range. optical signals generated by each channel group are passed to a multi-mode interference (mmi) coupler that multiplexes the channel group split across some number of output streams that may be limited to maintain sufficient output power for a given application. the odd channeled multiplexed signals and the even channeled multiplexed signals are passed to interleavers that generate a full spectrum output signal for each bank. output signals from all banks exit the pic through an output coupler.
Abstract: an apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. the first mating protrusion is to be partially disposed within a first recess formed in a second surface of a photonic integrated circuit (pic) die when the first surface of the optical interposer opposes the second surface of the pic die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the pic die. a first portion of an outer surface of the first mating protrusion is to contact a first side wall of the first recess and a second portion of the outer surface of the first mating protrusion is to oppose a second side wall of the first recess such that a second space is to be defined therebetween.
20250216636. OPTICAL BRIDGE PHOTONIC INTERPOSER PHOTONIC INTERPOSER COMMUNICATIONS (Intel)
Abstract: embodiments disclosed herein include photonics packages. in an embodiment, the photonics package comprises a substrate. in an embodiment, a first interposer is over the substrate, and a first die is on the first interposer. in an embodiment, a second interposer is over the substrate, and a second die is on the second interposer. in an embodiment, an optical bridge is between the first interposer and the second interposer.
Abstract: determining initial conditions for resolution enhancement technology (ret) processing of a new mask layer comprises reusing ret geometries from layout portions of previously ret-processed mask layers that match layout portions in the new mask layer. if the ret geometries comprise sub-resolution assist features (srafs), conflicts between srafs corresponding to neighboring matching layout portions can be resolved as part of determining the initial conditions. the initial conditions can also be based on ret geometries generated by machine learning models for layout portions of the new layer that closely match layout portions in previously processed mask layers. initial conditions for the remaining layout portions in the new mask layer are generated via ret processing. these initial conditions can enable faster ret processing runtime or reduced computing load for a given level of ret processing output quality.
Abstract: an integrated circuit (ic) device may include features that were patterned using overlapping exposure fields and that span the region of overlap between the exposure fields. the features may be developed from negative tone photoresist exposed using one or more clear-field reticles. a clear-field reticle may include a reflective substrate and absorber features in an opaque mask on the substrate. a single reticle may have complementary portions of an overlapping pattern, e.g., for a line feature, on opposite edges. complementary portions of an overlapping pattern may be on different reticles.
20250216827. SMART HOME FUNCTIONALITY AWARENESS USER TASKS (Intel)
Abstract: smart home functionality awareness may improve the ability for a smart home system to identify existing and absent smart home skills or smart home devices that may be used to perform a specific task requested by a user. this smart home functionality awareness improves the ability of a smart home system to identify an existing capability of the smart home system that addresses requested electronic device command. this smart home functionality awareness improves the ability of a smart home system to identify a recommended capability, where the recommended capability provides improved functionality over the existing capability for addressing the requested electronic device command. this recommended capability may be identified based on determining that existing capabilities are sufficient to accomplish a task with low performance, and further identify what additional resources may be needed to improve the ability of the smart home system to execute the requested electronic device command.
20250216849. SYSTEM METHOD AUTONOMOUS MOBILE ROBOT RELOCALIZATION (Intel)
Abstract: various aspects of methods, systems, and use cases include techniques for robotic relocalization. a robot may be configured to perform relocalization using operations to determine a cause of a loss of pose; use a nearest neighbor process to select a set of milestones from a roadmap when the cause of the loss of pose is due to a malfunction, or use a ranking process to select the set of milestones from the roadmap when the cause of the loss of pose is not due to the malfunction, the roadmap including a plurality of milestones; generate particle clouds around each milestone in the set of milestones; and perform localization on each milestone in the set of milestones to attempt to relocalize the robot.
20250216855. DYNAMIC MAP REGENERATION BASED SELF-LEARNING COOPERATION-BASED FEEDBACK (Intel)
Abstract: disclosed herein are devices, methods, and systems for map regeneration of an environment. the system includes a map manager configured to maintain a global map of the environment. the system also includes a robot configured to determine a correspondence between a mapped subarea of the environment and a global map of the environment and, based on the correspondence, transmit map data of the mapped subarea to a map manager. the map manager is configured to determine a quality metric of the map data of the mapped subarea with respect to the global map and update the global map with the map data of the mapped subarea based on the quality metric.
20250216859. EMERGENCY MANAGEMENT USING ROBOT FLEET (Intel)
Abstract: a server includes a memory on which a map is stored, wherein the map represents locations of a plurality of mobile units; and a processor, configured to generate an emergency response plan based on sensor data and the map, wherein the emergency response plan comprises actions to be taken by a plurality of robots within a vicinity of the mobile units; and instruct a transceiver to send a signal representing the emergency response plan.
Abstract: techniques and mechanisms for providing a power state wherein a temperature-based voltage regulation is disabled. in an embodiment, a load circuit receives one or more clock signals, and one or more supply voltages. power management logic facilitates either one of a first power state and a second power state, each for providing power to the load circuit. the first power state enables each clock signal provided to the load circuitry, and further comprises an enabled state of a functionality to perform inverse temperature dependency voltage regulation. the second power state disables each clock signal provided to the load circuitry, and further comprises a disabled state of the functionality. in another embodiment, during the second power state, each voltage supply provided to the load circuit is regulated in a respective voltage range which enables at least some state of the load circuit to be maintained.
20250216891. CLOCK LEADER MONITORING TIME-SYNCHRONIZED NETWORKS (Intel)
Abstract: various systems and methods for evaluating time synchronization values provided from a clock leader are discussed. an example method performed by a clock follower device includes: obtaining a timestamp from a time synchronization protocol that provides synchronized time values from a clock leader; determining, based on the timestamp, a measured time drift value that represents a time drift of a hardware clock, with the time drift observed relative to the clock leader; determining an estimated time drift value that models a time drift of the hardware clock, modeled from one or more environmental conditions experienced by the hardware clock; comparing the measured time drift value with the estimated time drift value; and adjusting a clock of the device based on the timestamp, in response to validating that the measured time drift value is within a statistically expected range corresponding to the estimated time drift value.
20250216905. TECHNOLOGIES ILLUMINATION INPUT/OUTPUT PORTS COMPUTE DEVICE (Intel)
Abstract: techniques for illumination of input/output (i/o) ports on a compute device are disclosed. in an illustrative embodiment, microholes are defined in a chassis around an opening in the chassis for an i/o port. a light-emitting diode (led) contained within the chassis can shine light on the microholes, which can pass through the microholes. a user of the compute device can see the light through the microholes, allowing the user to identify the location and type of the i/o port, even in dark or low-light conditions. in some embodiments, the leds used to illuminate the microholes may be the same leds that illuminate the keys of the keyboard, simplifying the design, construction, and control of illumination of the microholes.
20250216916. APPARATUS, SYSTEM METHOD PROVIDING POWER SETTING PROCESSOR (Intel)
Abstract: for example, a power-setting controller may be configured to provide a power setting for a processor based on one or more sensor-based inputs corresponding to one or more temperature sensors. for example, a sensor-based input corresponding to a temperature sensor may include a temperature input and a target temperature. for example, the power-setting controller may include one or more nnpid-based power controllers configured to provide one or more sensor-based power settings corresponding to the one or more temperature sensors. for example, an nnpid-based power controller of the nnpid-based power controllers may be configured to provide a sensor-based power setting corresponding to the temperature sensor based on the sensor-based input corresponding to the temperature sensor. for example, the nnpid-based power controller may include an nnpid controller configured to determine a temperature setting based on the temperature input and the target temperature corresponding to the temperature sensor.
20250216928. FEEDBACK REQUIRED SENSOR RESOLUTION ACCELERATION (Intel)
Abstract: a system for optimizing sensor data processing in a shared virtual environment can include a processor and a memory storing instructions. the instructions can be executable by the processor to cause the processing circuitry of the processor to receive context data indicative of a virtual environment interaction, determine a fidelity requirement for sensor data based on the context data, and adjust sensor data processing parameters to align an output fidelity with the fidelity requirement.
20250216932. Control device method controlling display unit vehicle (Intel)
Abstract: a control device and a method for controlling a display unit arranged in a vehicle, such that the control device comprises a processor configured to receive first data representing an environment of a vehicle; determine a driving trajectory of the vehicle using the first data; receive second sensor data representing a head movement of an occupant of the vehicle; determine a time-dependent relative movement between the head movement of the occupant and a vehicle movement according to the driving trajectory using a speed of the vehicle; determine a time-dependent change in a position of display information to be displayed on a display unit disposed in the vehicle such that the change in the position of the display information compensates for all or part of the relative movement; and generate control instructions for controlling the display unit to display the display information in accordance with the time-dependent change in the position.
20250217141. BFLOAT16 FUSED MULTIPLY INSTRUCTIONS (Intel)
Abstract: techniques for performing bf16 fma in response to an instruction are described. in some examples, an instruction has fields for an opcode, an identification of location of a packed data source/destination operand (a first source), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source/destination operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a bf16 value fused multiply-accumulate operation using the first, second, and third source operands and store a result in a corresponding data element position of the source/destination operand
20250217142. INSTRUCTIONS FUSED MULTIPLY-ADD OPERATIONS VARIABLE PRECISION INPUT OPERANDS (Intel)
Abstract: disclosed embodiments relate to instructions for fused multiply-add (fma) operations with variable-precision inputs. in one example, a processor to execute an asymmetric fma instruction includes fetch circuitry to fetch an fma instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched fma instruction, and a single instruction multiple data (simd) execution circuit to process as many elements of the second source vector as fit into an simd lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the simd lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.
20250217147. DEVICE, METHOD SYSTEM PROVIDE ACCESS RESOURCE PHYSICAL REGISTER FILE (Intel)
Abstract: techniques and mechanisms for allocating resources of a physical register file (prf) each to correspond to a respective logical register. in an embodiment, a prf comprises multiple physical registers (or âentriesâ) which each comprise a respective two or more minimum allocable sub-portions. for a given one such entry, the minimum allocable sub-portions of the entry are available to be allocated either individually or in combination with each other. allocation of a given one or more sub-portions of a prf entry enables functionality of a corresponding logical register with said one or more sub-portions. at a given time, logical registers of different respective capacities are implemented with corresponding entry portions of the same prf. in another embodiment, a bitmap facilitates a search to identify an availability of one or more prf entry portions for allocation to correspond to a logical register.
20250217149. APPARATUSES, METHODS, SYSTEMS INSTRUCTIONS MATRIX TRANSPOSE (Intel)
Abstract: examples detailed herein at least include transpose circuitry that is external to a matrix operations accelerator. in some examples, the transpose circuitry at least includes a plurality of transpose engines to transpose a source matrix operand of a single instruction to generate a transposed source matrix, and control circuitry to direct the plurality of transpose engines to alternately operate in a parallel loading mode and a serial loading mode to generate the transposed source matrix, wherein the plurality of transposes engines and the control circuitry are at least a portion of transpose circuitry.
20250217155. EARLY RESTEERING MISPREDICTED BRANCHES (Intel)
Abstract: techniques for early resteering of a branch misprediction are described. examples detailed herein use a virtual run-ahead mechanism in the core. on a branch misprediction for an hard-to-predict (h2p) branch, a subset of the backslice of the h2p branch are replayed from the out-of-order engine directly (while the main thread is flushing and restarting execution from the front-end).
20250217157. SOFTWARE DEFINED SUPER CORES (Intel)
Abstract: techniques for software defined super core usage are described. in some examples, a first and second processor core are to operate as a single virtual core enabled by the operating system to fetch the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using flow control instructions that have been inserted into the single threaded program.
20250217160. SOFTWARE DEFINED SUPER CORES (Intel)
Abstract: techniques for software defined super core usage are described. in some examples, in super core mode each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently.
20250217288. REGISTER RENAMING CACHING (Intel)
Abstract: techniques for register renaming caching are described. in an embodiment, an apparatus includes a register renaming cache, front-end circuitry, lookup circuitry, and execution circuitry. the register renaming cache is to store register renaming information associated with an instruction trace. the register renaming information is to be learned from a first execution of the instruction trace and is to be used to perform register renaming in connection with a second execution of the instruction trace. the front-end circuitry is to provide, based on the instruction trace, operations for execution. the lookup circuitry to look in the register renaming cache for entries corresponding to the operations. the execution circuitry is to execute the instruction trace.
Abstract: a processor of an aspect includes a cache hierarchy and a memory access unit coupled with the cache hierarchy. the memory access unit is to perform a demand load based on a y-bit pointer to cause a first one or more cache lines to be loaded from memory into the cache hierarchy. the y-bit pointer has an x-bit virtual address field and a data object extent field in one or more of bits [y-1:x]. the data object extent field is to store a value. the processor also includes a prefetch unit coupled with the cache hierarchy. the prefetch unit is to determine whether or not to prefetch a second one or more cache lines, adjacent to the first one or more cache lines, from memory into the cache hierarchy based at least in part on the value. in another aspect, the prefetch unit may additionally or alternatively scan code or data for a bit pattern in bits [y-1:x] to identify likely pointers and prefetch data referenced by such identified pointer's memory addresses. other processors, methods, systems, and instructions are disclosed.
20250217295. PARTITIONING AND/OR GRADUAL RE-KEYING RANDOMIZED CACHES (Intel)
Abstract: techniques for partitioning and/or gradual re-keying of randomized caches are described. in certain examples, an apparatus includes an execution circuit to cause a memory access request; a cache to store a plurality of sets, each of the sets to include a plurality of cache lines; and a cache randomizer circuit to generate a randomized index into the plurality of sets of the cache based on an address of the memory access request by encrypting a first subset of bits of the address of the memory access request to generate an encrypted value, and generating the randomized index based on a first subset of bits of the encrypted value. the encrypting is to be based on a first key for a first segment of the cache and a second segment of the cache during a first period, on a second key for the first segment of the cache and the first key for the second segment of the cache during a second period, and on the second key for the first segment of the cache and the second segment of the cache during a third period.
20250217305. IO FABRIC PERFORMANCE MANAGEMENT (Intel)
Abstract: in some embodiments, traffic detection circuits are provided to increase an io fabric frequency when increased io device traffic is detected.
20250217312. CMOS COMPATIBLE MATRIX COMPUTING NETWORK (Intel)
Abstract: techniques are disclosed for implementing a cmos-compatible millimeter wave matrix computing network architecture, which enables high-speed matrix operations for deep learning neural networks through a reconfigurable feedforward architecture using matrix computing meshes. each mesh may include hybrid couplers and adjustable phase shifters. the architecture may be configured in various arrangements with programmable weights. the architecture offers advantages over existing solutions through full cmos compatibility, the elimination of optical-electrical conversion, improved scalability, total latency, and superior power efficiency. applications include massive mimo systems and cognitive radar, in which the network may be implemented as part of rf front ends to reduce adc requirements, system complexity, and power consumption.
Abstract: an apparatus of an aspect includes a context storage to store context of a logical processor, and an execution unit coupled with the context storage. the execution unit to perform operations corresponding to a control primitive or an exceptional condition. the operations including to selectively save a first subset of the context, from a first subset of the context storage written to after entrance into a protected execution environment, to system memory, and cause the logical processor to exit the protected execution environment. other apparatus, methods, systems, and instructions are disclosed.
Abstract: an apparatus may include a processor, the processor configured to: access a container cryptographically bound to a component of a digital entity, wherein the container comprises information representative of a compliance of the digital entity to cybersecurity requirements, wherein the component of the digital entity comprises a hardware component or a software component; determine, based on the information, a result representing whether the digital entity is compliant with the cybersecurity requirements; determine, based on the result, a verification state of the digital entity.
20250217561. SEMICONDUCTOR TEST STRUCTURE GENERATION BASED LITHOGRAPHIC SIMULATION (Intel)
Abstract: a method comprising accessing, by at least one computing system, a plurality of layout blocks comprising a plurality of design patterns for an interconnect layer and identifications of lithography risk sites of the plurality of design patterns, the lithography risk sites corresponding to violations of constraint based checks for simulated physical patterns corresponding to the plurality of design patterns; and generating, by the at least one computing system, a layout comprising the plurality of layout blocks and at least one routing path that is coupled to a subset of the plurality of design patterns having lithography risk sites.
20250217570. RULE PLATFORM SEMICONDUCTOR MANUFACTURING (Intel)
Abstract: a method comprising receiving, at a computing system, a request for design rules of an integrated circuit technology node; and providing, by the computing system, a plurality of design rule entries for display in a tabular format by an interface, the plurality of design rule entries selected based on the request, a design rule entry of the plurality of design rule entries corresponding to a design rule of the plurality of design rules, the design rule entry comprising a first cell designated for a label of the design rule, a second cell designated for a description of the design rule, and a third cell designated for a numerical dimension for the design rule.
20250217627. WEIGHT ROUNDING OPTIMIZATION VIA SIGNED GRADIENT DESCENT (Intel)
Abstract: systems, apparatuses and methods may provide for technology that determines a tensor based on a signed gradient descent value and modifies a rounding operation with respect to weights in a large language model (llm) based on the tensor. the rounding operation may be modified on a per block basis.
20250217882. Systems, Apparatuses, Methods Resource Bandwidth Enforcement (Intel)
Abstract: systems, methods, and apparatuses for resource bandwidth monitoring and control are described. for example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.
20250217925. DISTRIBUTED IMAGE SCALING (Intel)
Abstract: image scaling processes that work on an entire region of interest at once or in a serial manner can be computationally expensive and slow, especially for high-resolution images. to address this issue, distributed image scaling can be performed to improve real-time performance. distributed image scaling involves dividing a region of interest of an image into sub-regions and scaling them in parallel using multiple scaler cores. the workloads to the parallel scaler cores include precise alignment information to avoid artifacts at sub-region boundaries in the scaled image.
20250217951. LOCAL ADAPTIVE CONTRAST ENHANCEMENT TECHNIQUES (Intel)
Abstract: in one embodiment, an apparatus includes hardware circuitry to determine a tile brightness value and a tile contrast value for each respective tile of a plurality of tiles that together comprise an input frame. the circuitry obtains a first enhancement factor (e.g., from a first lookup table) based on the tile brightness value and a second enhancement factor (e.g., from a second lookup table) based on the tile contrast value. the circuitry generates an output frame based on the first enhancement factor and the second enhancement factor.
20250217962. METHODS APPARATUS DETECT DEFECTS GATE-ALL-AROUND TRANSISTOR ARCHITECTURES (Intel)
Abstract: systems, apparatus, articles of manufacture, and methods to detect defects in gate-all-around transistor architectures are disclosed. an apparatus includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: determine a first contrast to noise ratio (cnr) in a first image of a location on a semiconductor wafer; determine a second cnr in a second image of the location on the semiconductor wafer; and determine whether the location includes a buried defect based on the first cnr and the second cnr.
20250217997. POWER-EFFICIENT VIDEO CONFERENCING (Intel)
Abstract: unique characteristics of a video in video conferencing can be exploited for power savings by reducing the rate of processing of a background. the background, if sufficiently static enough, the signal processing of the background can be skipped to save power. skipping the background means the signal processing processes a cropped image having the foreground only. as a result, the foreground would be processed by the signal processing at a full frame rate, while the background is processed at a reduced frame rate. optionally, the processed cropped image can be blended with a stored image. optionally, the processed cropped image can be output without blending.
Abstract: this disclosure describes systems, methods, and devices related to latency-adaptive viewport prediction for use in viewport-dependent content streaming. a method may include identifying, by a virtual reality (vr) or augmented reality (ar) device, first viewport data used by and received from a display device; generating a first estimated compensation latency based on at least one of a first network latency and by the processing circuitry, from among multiple candidate viewport prediction models each using a different respective time interval, a first viewport prediction model based on a comparison of the first estimated compensation latency to a first time interval used by the first viewport prediction model; generating, using the first viewport prediction model and the first viewport data, a first viewport prediction; and selecting, based on the first viewport prediction, a first content tile for rendering by the display device.
20250218147. Background Segmentation System (Intel)
Abstract: a system includes a processor configured to determine a first image of a first capture area including one first image element associated with first image element coding information classified as erroneous; determine a second image of a second capture area, the first capture area and the second capture area overlapping in an overlap area; determine a second image element spatially corresponding to the first image element in the second image, wherein the first image element and the second image element represent a part of the overlap area; determine substitute image element coding information for the first image element of the first image using second image element coding information associated with the second image element of the second image that is not classified as erroneous; and associate the determined substitute image element coding information with the first image element of the first image to obtain a first substitute image.
20250218198. Information system method controlling information system (Intel)
Abstract: an information system for a vehicle includes a processor configured to: determine system information representing one or more than one message relating to an occupant of the vehicle and/or the vehicle and/or an environment of the vehicle; determine a current driving task of the vehicle; determine, using sensor data representing a state of the driver of the vehicle, driver information representing a physical and/or mental state of the driver; determine, using the current driving task and the driver information, message presentation information indicating, for each of the one or more than one message, whether the message is to be presented to the driver and/or how the message is to be presented to the driver and/or at what time the message is to be presented to the driver; and generate control instructions to control at least one component of the vehicle according to the message presentation information.
20250218215. Dynamic Target Detection Tracking (Intel)
Abstract: a device includes a memory, configured to store an identifier corresponding to a target; and a processor, configured to send the identifier to one or more first robots; instruct the one or more first robots to search for the target using the identifier, receive a position of the target from a first robot of the one or more first robots; and instruct a second robot to travel to the position.
20250218279. AUTOMATICALLY STAGED HARDWARE-SWAPPING APPARATUS (Intel)
Abstract: an apparatus is configured to generate control signals used for swapping critical hardware (e.g., a first circuit and a second circuit) in-and-out from an active communication channel for off-line calibration without disturbance to live data transmission on the communication channel. additionally, the apparatus is configured to enable uninterrupted transmission on the communication channel without the use of a digital state-machine controller to stage the swapping. the staging function of the apparatus is accomplished organically, to secure gap-free transmission during the swapping. in operation, control signals are generated based on a single exchange signal. the control signals are used to turn on and off multiple switches to enable swapping between the first circuit and the second circuit in and out of the communication channel, achieving a low ber and a continuously connected data path without a time gap and interruptions in the data transmission.
Abstract: techniques and mechanisms for selectively throttling operation of circuitry, wherein said throttling is based on a threshold rate at which a memory is to be refreshed. in an embodiment, a power management unit (pmu) accommodates coupling to receive an identifier of a first refresh rate which has been requested with the random access memory (ram) device. the pmu provides functionality to calculate a difference between a threshold maximum refresh rate and the first refresh rate. based on the calculated difference, a throttle action is identified, and one or more control signals are generated to throttle operation of circuitry which is thermally coupled with the ram device. in another embodiment, the ram device continues to be refreshed at the first refresh rate during and/or after the throttling of the circuitry.
Abstract: a bist (built-in self-test) adaptive port (bap) interface enables an in-field mbist (memory bist). the bap enables non-destructive testing of the memory locations. the bap includes registers to store contents of the memory device during the in-field mbist on the memory device. the bap can store the starting address of the next infield periodic testing and operational data from a selected memory address in the registers while the mbist controller performs the test on the memory address. the system can then restore the operational contents of the memory after the test is complete.
20250218652. CROSS-CONNECTED COUPLED INDUCTOR STRUCTURES (Intel)
Abstract: cross-connected coupled inductor structures are disclosed herein. an example coupled inductor includes an enclosure having a left section and a right section, a front surface opposite a back surface, and a top surface opposite a bottom surface, a first plane of the front and back surfaces orthogonal to a second plane of the top and bottom surfaces. the example coupled inductor also includes a first conductor having a first terminal proximate to an intersection of the bottom surface and the front surface of the right section of the enclosure, and a second terminal proximate to an intersection of the bottom surface and the back surface of the left section of the enclosure. the example coupled inductor also includes a second conductor having a third terminal proximate to an intersection of the bottom surface and the front surface of the left section of the enclosure, and a fourth terminal proximate to an intersection of the bottom surface and the back surface of the right section of the enclosure.
20250218678. DIE WITHIN HOLE SUBSTRATE CORE ATTACHED METAL FEATURES OVER HOLE (Intel)
Abstract: an apparatus comprises a substrate core comprising a hole extending from an opening at a first surface of the substrate core to a second surface opposite the first surface. a metal layer is over the first surface. the metal layer comprises a plurality of first metal features over a first portion of the opening. the metal layer also includes a second metal feature extending from a sidewall of the hole and over a second portion of the opening. a die is within the hole and coupled to the first metal features by solder features. the die may comprise a capacitor.
Abstract: systems, apparatus, articles of manufacture, and methods to modify carbide surfaces in semiconductor device fabrication processes are disclosed. an example apparatus includes a semiconductor substrate; a layer of carbide on the substrate; and a surface treatment covalently bonded to a surface of the carbide, the surface treatment including at least one of nitrogen or carbon.
Abstract: techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. the techniques include a mid-process removal of one or more partially-formed fins. the resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). in an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. one or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). after fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. a liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.
20250218847. CONFIGURABLE CARRIER TRANSFER SELF-ASSEMBLY MULTIPLE INTEGRATED CIRCUIT DEVICES (Intel)
Abstract: a first carrier comprises a plurality of regions. each region comprises a first zone and a second zone. the second zone comprises a portion that surrounds the first zone. each first zone comprises a hydrophilic surface, and each second zone comprises a hydrophobic surface. a first liquid is deposited on the first carrier. the plurality of regions are aligned with a plurality of dies on a second carrier. the dies are transferred from the second carrier to the first carrier. a second liquid is deposited on a substrate, which includes a plurality of bond areas. each die bond area comprises a hydrophilic surface. the dies are transferred from the first carrier to the substrate.
20250218868. SELF-ALIGNED INTERCONNECT FEATURES FLOATING DIELECTRIC STRUCTURE (Intel)
Abstract: an integrated circuit device includes (i) a first interconnect feature extending within a first dielectric material, and (ii) a second interconnect feature extending within the first dielectric material, and landing on the first interconnect feature. the integrated circuit device further includes a layer having a first section and a second section, wherein the layer includes a second dielectric material that is compositionally different from the first dielectric material. an opening between the first section and the second section is above, and vertically aligned to, the first interconnect feature. the second interconnect feature extends through the opening. in an example, each of the first section and the second section is vertically separated from the first interconnect feature by at least 2 nanometers (nm). in an example, a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material by at least 5%.
20250218869. SELF-ALIGNED BACK-SIDE GATE VIAS (Intel)
Abstract: transistor structures between and coupled to front- and back-side interconnect layers may have precisely aligned arrays of contacts and dielectric structures over and under the transistor structures. back-side dielectric plugs may electrically isolate source and drain regions contacted on the front side from back-side interconnect lines. back-side dielectric plugs may have a seam indicating plug formation from the back side, and the seam may be on a side contacting a back-side interconnect line. spacer layers may insulate back-side gate contacts from adjacent back-side contacts. contacts and dielectric structures on a back side may be formed using directed self-assembly of sacrificial materials aligned to sacrificial structures on source and drain regions and revealed on a substrate back side.
20250218879. RESIST TENTING PLATING CORE CAVITY COMPONENT ATTACHMENT (Intel)
Abstract: embodiments disclosed herein include components that are embedded within a core of a package substrate. in an embodiment, the component is supported on a pad provided at a bottom of a cavity through the core. in an embodiment, such an apparatus may comprise a substrate with a cavity through a thickness of the substrate. in an embodiment, the cavity comprises sidewalls. in an embodiment, a layer spans an opening of the cavity, and the layer covers at least a portion of the sidewalls of the cavity. in an embodiment, a component is coupled to the layer, and the component is at least partially within the cavity.
20250218880. MICROELECTRONIC ASSEMBLIES PILLAR-FIRST CONDUCTIVE VIA FORMATION GLASS CORES (Intel)
Abstract: methods for fabricating glass cores with conductive vias (e.g., tgvs), as well as related devices, are disclosed. methods described herein are based on fabricating pillars of conductive materials (e.g., metals or metal alloys) on a temporary support, inserting the pillars into corresponding via openings in a glass core, and at least partially filling the remaining space in the openings with a filler material.
20250218881. LIQUID-BASED METHOD EMBEDDING COMPONENTS THICK SUBSTRATES (Intel)
Abstract: embodiments disclosed herein include components embedded in a core of a package substrate. embodiments disclosed herein may include an apparatus that comprises a substrate with a cavity through a thickness of the substrate. in an embodiment, a component is in the cavity, and a first layer is in the cavity and contacts a sidewall of the component. in an embodiment, the first layer comprises a first material composition. in an embodiment, a second layer is over the first layer, and the second layer comprises a second material composition that is different than the first material composition.
20250218885. PATTERNED MOLD UNDERFILL (MUF) FILMS DEEP TRENCH FILLING (Intel)
Abstract: embodiments disclosed herein include components that are embedded in the core of a package substrate. in an embodiment, such an apparatus comprises a substrate with a cavity through a thickness of the substrate. in an embodiment, a component is in the cavity, and a first layer is in the cavity. in an embodiment the first layer is a dielectric material. in an embodiment, a second layer is in the cavity, and the second layer is a dielectric material that is a different material than the second layer.
20250218888. WAFER TRIM EDGE PROTECTION (Intel)
Abstract: wafer trim edge protection is described. in an example, an integrated circuit structure includes a substrate having a feature including copper therein or thereon, the substrate having a recessed sidewall. a first layer including silicon and oxygen above the feature including copper. a burr including copper extending from the feature including copper and along the recessed sidewall of the substrate, along a side of the first layer including silicon and oxygen, and on a top of the first layer including silicon and oxygen. a layer including silicon and nitrogen is below or above the first layer including silicon and oxygen. a second layer including silicon and oxygen above the layer including silicon and nitrogen, wherein the second layer including silicon and oxygen encapsulates the burr including copper.
20250218898. RECONSTITUTED PASSIVE MECHANICAL SUPPORT STRUCTURES (Intel)
Abstract: embodiments disclosed herein include components that include passive electrical devices with a thickness augmentation. in an embodiment, such an apparatus comprises a substrate with a first material composition, and a liner on a sidewall of the substrate. in an embodiment, a layer is on the substrate, where the layer has a second material composition that is different than the first material composition. in an embodiment, the layer directly contacts at least a portion of a surface of the substrate.
20250218901. BACKSIDE CONTACT PLACEHOLDER FORMATION IMPROVED PROCESS CONTROL (Intel)
Abstract: devices, transistor structures, systems, and techniques are described herein related to backside contacts for field effect transistors formed using a backside placeholder contact. the backside placeholder contact is templated from a recessed dielectric material such as a recessed carbon hardmask. the recessed dielectric material is formed and replaced with a placeholder metal in frontside processing, and the placeholder metal is revealed and replaced from the transistor backside to form the backside contact.
20250218904. TECHNOLOGIES POWER SPACER COMPONENTS EMBEDDED SUBSTRATE CORE (Intel)
Abstract: technologies for components embedded in a substrate core are disclosed. in one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. a spacer may be included between the power components. the power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
20250218905. COMPONENT COUPLED CONDUCTIVE VIAS ENCAPSULATED ELECTRONIC SUBSTRATE (Intel)
Abstract: an apparatus includes a substrate, a cavity within the substrate, and a die within the cavity. the substrate has an exterior surface. the cavity includes a first surface and a second surface opposite the first surface. the die includes a discrete component, a first side, a second side opposite the first side, and conductive features at the first side. in an embodiment, a bond film is between the first surface and the first side. a plurality of conductive vias extend from the exterior surface through the substrate and bond film to the conductive features. in an embodiment, the bond film may be omitted. the plurality of conductive vias extend from the exterior surface through the substrate. the conductive features of the die are coupled with the conductive vias by solder features, and the second side of the die is spaced away from the second surface.
20250218906. RECONSTITUTED PASSIVE ASSEMBLIES EMBEDDING THICK CORES (Intel)
Abstract: embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. in an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. in an embodiment the substrate comprises a passive electrical device. in an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. in an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.
20250218909. ENVIRONMENTAL SEALING ELECTRONICS CHIP PACKAGE SOCKETS (Intel)
Abstract: embodiments disclosed herein include socketing apparatuses with environmental sealing options. in an embodiment, such an apparatus comprises a first substrate, and a second substrate over the first substrate. in an embodiment, a socket structure is provided between the first substrate and the second substrate, where the socket structure comprises a plurality of electrical interconnects between the first substrate and the second substrate. in an embodiment, a die is over the second substrate, and a third substrate is over the die. in an embodiment, a ring is around the socket structure, and the ring is coupled to the first substrate and the third substrate.
Abstract: in embodiments herein, a surface finish (sf) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. in some embodiments, the sf may be electroless nickel-electroless palladium-immersion gold (enepig). in other embodiments, the sf may be immersion gold-electroless palladium-immersion gold (igepig). in other embodiments, the sf may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
Abstract: in embodiments herein, a surface finish (sf) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. in some embodiments, the sf may be electroless nickel-electroless palladium-immersion gold (enepig). in other embodiments, the sf may be immersion gold-electroless palladium-immersion gold (igepig). in other embodiments, the sf may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
20250218915. PEDESTAL STRUCTURE PASSIVE CIRCUIT COMPONENT STRUCTURE (Intel)
Abstract: an apparatus comprising a package substrate comprising a core layer; a pedestal embedded in the core layer; and a structure comprising a passive circuit component, wherein the structure is above the pedestal and is embedded in the core layer.
Abstract: in embodiments herein, a surface finish (sf) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. in some embodiments, the sf may be electroless nickel-electroless palladium-immersion gold (enepig). in other embodiments, the sf may be immersion gold-electroless palladium-immersion gold (igepig). in other embodiments, the sf may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
Abstract: in embodiments herein, a surface finish (sf) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. in some embodiments, the sf may be electroless nickel-electroless palladium-immersion gold (enepig). in other embodiments, the sf may be immersion gold-electroless palladium-immersion gold (igepig). in other embodiments, the sf may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
20250218926. MICROELECTRONIC ASSEMBLIES INCLUDING CAVITY-LESS ENCAPSULATED DIES (Intel)
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a substrate having a material and conductive pathways through the material, wherein the material includes an organic dielectric material; and a microelectronic component having a first surface and an opposing second surface, wherein the first surface of the microelectronic component is electrically coupled to the conductive pathways in the material by interconnects, wherein the interconnects include solder and are surrounded by a capillary underfill material, and wherein the microelectronic component and the capillary underfill material are surrounded by the material of the substrate.
20250218928. TRENCH CAPACITOR INTERCONNECT REGION (Intel)
Abstract: techniques are provided herein for forming one or more mim trench capacitors in the interconnect region above the device layer of an integrated circuit. in an example, the mim trench capacitor(s) are formed within one of the upper interconnect layers of the interconnect region, and thus can have a relatively high height (e.g., greater than about 200 nm). an interconnect layer included in a stack of interconnect layers includes a mim capacitor having a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. the mim capacitor runs along the outside surface of a plurality of dielectric fins, which greatly increases the surface area of the capacitor within a relatively small plan footprint. the first and second electrodes may connect with one or more topside contacts and/or one or more buried conductive lines.
20250218929. EMBEDDED DEEP TRENCH CAPACITORS INTEGRATED CIRCUIT DEVICE PACKAGE SUBSTRATES (Intel)
Abstract: an apparatus is provided which comprises: a substrate core comprising a first core layer and a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and a second circuit component embedded entirely within a cavity in the second core layer, wherein the second circuit component and the second core layer have substantially equivalent heights. other embodiments are also disclosed and claimed.
20250218931. INTERCONNECT VIA INDUCED ASYMMETRIC PROFILE (Intel)
Abstract: techniques are provided herein for forming a via with an asymmetrically flared profile within the interconnect region over semiconductor devices. in some examples, a via within the interconnect layer has a greater critical dimension (cd), or top surface width, along a first direction (e.g., along an x-axis) than it has along a second direction orthogonal to the first direction (e.g., along a y-axis). the bottom surface of the via may have substantially the same width along both the first and second directions, such that the width of the via tapers or steps inward between the top surface width along the first direction and the bottom surface width along the first direction. there is little to no tapering or step of the via between the top surface width along the second direction and the bottom surface width along the second direction.
20250218937. DIRECTED SELF ASSEMBLY-ENABLED BACK-SIDE CONTACT ARRAYS ALIGNED GATE ELECTRODES (Intel)
Abstract: transistor structures between and coupled to front- and back-side interconnect layers may have precisely aligned arrays of contacts and dielectric structures over and under the transistor structures. transistor structures may have a gate electrode thickness under a channel region one-and-a-half or two times greater than a thickness between adjacent nanoribbons in the channel region. front- and back-side spacer layers with a same composition may have a discernible interface. contacts and dielectric structures on a back side may be formed using directed self-assembly of sacrificial materials aligned to gate electrodes revealed on a substrate back side.
20250218942. VIA ALIGNED ADJACENT INTERCONNECT LAYERS (Intel)
Abstract: a method comprising forming a first layer, forming a second layer over the first layer, and applying an etch material to concurrently form a first interconnect line and a second interconnect line in the first layer and side surfaces of a first via and a second via in the second layer, wherein a side surface of the first via is seamless with a side surface of the first interconnect line, wherein a side surface of the second via is seamless with a side surface of the second interconnect line, wherein the first via is adjacent to the second via.
20250218949. TECHNIQUES FORM INTEGRATED CIRCUIT STRUCTURES CONDUCTIVE INTERCONNECTS (Intel)
Abstract: a fabrication method and associated integrated circuit (ic) structures and devices that include conductive interconnects are described. in one example, techniques for forming conductive interconnects include use of a barrier layer (e.g., in a damascene process) and hard mask removal techniques using a dry etch process with fluorine radicals, which may improve the resistive-capacitive (rc) delay performance in resulting ic structures. in one example, an ic structure includes a first layer including a device contact structure and a second layer over the first layer. in one such example, the second layer includes a conductive interconnect coupled with the device contact structure, and one or more insulator materials surrounding the conductive interconnect, where the one or more insulator materials include fluorine at sidewalls of the conductive interconnect.
20250218952. SPACER EMBEDDED COMPONENT CORE (Intel)
Abstract: embodiments disclosed herein include components that are embedded within a core of a package substrate. in an embodiment, such an apparatus may comprise a substrate with a first surface and a second surface opposite from the first surface. in an embodiment, a cavity is provided through a thickness of the substrate, and a first layer is in the cavity. in an embodiment, the first layer has a first width. in an embodiment, a component is on the first layer, and the component has a second width that is smaller than the first width. in an embodiment, a second layer is provided between a sidewall of the cavity and a sidewall of the component.
Abstract: example methods and apparatus for embedding interconnect bridges having through silicon vias in substrates are disclosed. an example semiconductor package a bridge die disposed in a recess of an underlying substrate, the bridge die including a via that electrically couples a first contact on a first side of the bridge die and a second contact on a second side of the bridge die, the recess extending to a first surface of the underlying substrate; a bond material to electrically and mechanically couple the first contact and an interconnect of the underlying substrate; and a fill material positioned between the first side of the bridge die and the first surface of the underlying substrate.
20250218955. MICROELECTRONIC STRUCTURES INCLUDING EMBEDDED GLASS PATCH INTEGRATED CAPACITOR (Intel)
Abstract: microelectronic integrated circuit package structures include an apparatus having a a glass substrate embedded within a package substrate. the glass substrate comprises one or more trenches extending within a first portion, the one or more trenches comprising a first conductive layer on individual trench sidewalls, a dielectric layer on the first conductive layer and a second conductive layer on the dielectric layer. a second portion of the glass substrate is below the first portion.
20250218956. METHODS APPARATUS MOUNTING SEMICONDUCTOR DEVICES CAVITIES (Intel)
Abstract: methods and apparatus for mounting semiconductor devices in cavities are disclosed herein. an example semiconductor package includes a package substrate core having a cavity positioned therein; a pedestal positioned within the cavity of the core, the pedestal including a conductive material; and a capacitor disposed within the cavity, the capacitor positioned on the pedestal.
20250218957. METHODS APPARATUS EMBED SEMICONDUCTOR DEVICE GLASS CORE (Intel)
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to embed a semiconductor device in a glass core. an example apparatus comprises a package substrate comprising a glass core having a cavity in an outer surface of the glass core, the outer surface defining a first plane, and a semiconductor die attached to a surface of the cavity, the semiconductor die having contact pads on a surface of the semiconductor die, the contact pads arranged in a second plane, the second plane substantially coplanar with the first plane.
20250218958. PEDESTALS SEMICONDUCTOR COMPONENTS EMBEDDED PACKAGE SUBSTRATES RELATED METHODS (Intel)
Abstract: pedestals for semiconductors embedded in package substrates and related methods are disclosed. an example package substrate for an integrated circuit package disclosed herein includes core having a first surface, a second surface, and a cavity formed in the first surface, a semiconductor component disposed in the cavity, and a pedestal disposed in the cavity, the pedestal having a third surface coupled to the semiconductor component, and a fourth surface adjacent to the first surface, the pedestal dimensioned such that a first thickness of the pedestal and semiconductor is substantially equal to a second thickness of the core.
20250218959. PAD DESIGN EMBEDDED INTERCONNECT BRIDGES PACKAGE SUBSTRATES (Intel)
Abstract: semiconductor chip package substrates having interconnect bridges, assemblies including these semiconductor chip package substrates, and methods of manufacturing interconnect-bridge-containing semiconductor package chip substrates are provided. the interconnect bridges can include through-bridge vias that are electrically coupled to the semiconductor package substrate. the embedded bridges can be aligned to fiducials within the semiconductor package substrate.
20250218960. METHODS APPARATUS EMBED SEMICONDUCTOR DEVICES CORES PACKAGE SUBSTRATES (Intel)
Abstract: systems, apparatus, articles of manufacture, and methods to embed semiconductor devices in cores of package substrates are disclosed. an example package substrate includes a core having a first surface and a second surface. the core includes a cavity extending between the first and second surfaces. the example package substrate further includes a semiconductor die within the cavity; a pedestal within the cavity; and an adhesive within the cavity. the adhesive surrounds the semiconductor die and the pedestal. a material of the pedestal different from a material of the adhesive.
Abstract: an apparatus includes a package substrate comprising a core having a first surface along a first plane and a second surface along a second plane, a semiconductor device disposed within an opening in the core, the semiconductor device having a third surface along a third plane and a fourth surface along a fourth plane, the third plane substantially parallel to the first plane, a first dielectric material disposed on the first surface of the core, the first dielectric material extends into the opening to fill a first gap between a wall of the opening and a lateral surface of the semiconductor device, and a second dielectric material disposed on the second surface of the core, the second dielectric material extends into the opening to fill a second gap between the second plane and the fourth plane.
20250218962. TECHNOLOGIES STACK COMPONENTS EMBEDDED SUBSTRATE CORE (Intel)
Abstract: technologies for components embedded in a substrate core are disclosed. in one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. the power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. the stack may include, e.g., three or more power components. through-silicon vias in some or all of the power components can allow for connections through one power component to another. configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
20250218963. DIE CONDUCTIVE VIAS EMBEDDED SUBSTRATE (Intel)
Abstract: an apparatus includes a substrate core, which has a first height between a first surface and a second surface opposite the first surface. a die is within the substrate core. the die may include a deep trench capacitor. the die has a second height between a first side of the die and a second side opposite the first side. the first height is greater than the second height. a plurality of conductive vias extend from a plurality of conductive contacts at the first side of the die to the first surface of the substrate core. a material comprising a dielectric is disposed over the die and encapsulates the plurality of conductive vias. in some embodiments, a bond film is in contact with the second side of the die.
20250218964. TECHNOLOGIES CONNECTED COMPONENTS EMBEDDED SUBSTRATE CORE (Intel)
Abstract: technologies for connected components embedded in a substrate core are disclosed. in one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. the power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. through-silicon vias in some or all of the power components can allow for connections through one power component to another. configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
20250218965. SELF ALIGNMENT STRUCTURES INTERCONNECT BRIDGES (Intel)
Abstract: assemblies that include package substrates and semiconductor chips are provided. the package substrates include interconnect bridges having through-bridge vias. the assemblies also include alignment features and receiving cavities.
20250218982. TECHNOLOGIES CERAMIC COMPONENTS EMBEDDED SUBSTRATE CORE (Intel)
Abstract: technologies for components embedded in a substrate core are disclosed. in one embodiment, power components such as deep trench capacitors and multi-layer ceramic capacitors (mlccs) are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. the power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
Abstract: microelectronic integrated circuit package structures include one or more trench capacitors extending through a portion a device structure. the device structure is embedded within a portion of a core layer of a multi core package substrate, wherein one or more conductive interconnect structures are coupled with the one or more trench capacitors. a thickness of the device structure is equal to a thickness of the core layer.
20250218984. ENCAPSULATION TECHNIQUES COMPONENTS EMBEDDED CORE LAYER PACKAGE SUBSTRATE (Intel)
Abstract: in embodiments herein, a circuit component (e.g., a deep trench capacitor) is embedded within a core layer of a substrate. the circuit component may be encapsulated by multiple (e.g., two) layers of dielectrics or by a polymer material.
20250218988. DIRECT BOND INTERCONNECT ARCHITECTURES PACKAGING ASSEMBLIES (Intel)
Abstract: assemblies and methods of manufacturing assemblies comprising semiconductor chips and package substrates wherein the semiconductor chips are operably coupled to the package substrate through a solderless direct metal-to-metal bond region. the solderless direct metal-to-metal bond region also comprises a dielectric polymer. package substrates can comprise interconnect bridges and the semiconductor chips can be operably coupled to the interconnect bridges and can also be operably coupled to each other through the interconnect bridges.
Abstract: solder materials, solder balls, and solder features, and microelectronic devices and systems deploying the solders are discussed. a solder ball includes an inner core that is an alloy of tin, silver, and copper, which has a relatively high melting point. surrounding the inner core is a shell or cladding of a tin-bismuth alloy having a lower melting point. an optional nickel coating is on the inner core and between the inner core and the shell or cladding. during surface mount, the lower melting point the tin-bismuth alloy is used as the reflow temperature.
20250218998. LOW TEMPERATURE SOLDER INTERCONNECT PACKAGE PITCH SCALING (Intel)
Abstract: embodiments disclosed herein include an apparatus that comprises a first substrate and a second substrate over the first substrate. in an embodiment, an array of interconnects is provided between the first substrate and the second substrate. the array of interconnects comprises a first interconnect with a first material composition, and a second interconnect with a second material composition that is different than the first material composition.
20250218999. PASSIVE COMPONENT ASSEMBLY THICKNESS MODIFICATION MATCH CORE THICKNESS (Intel)
Abstract: embodiments disclosed herein include passive electrical components with thickness modifications. in an embodiment, such an apparatus may comprise a first substrate with a first material composition, where the first substrate comprises a passive electrical device. in an embodiment, a second substrate is coupled to the first substrate, where the second substrate has a second material composition. in an embodiment, a layer is over a surface of the second substrate opposite from the first substrate, and the layer is electrically insulating.
20250219002. ELECTROLYTIC INDIUM-PALLADIUM-GOLD AS SURFACE FINISH EMBEDDED DIE ATTACHMENTS (Intel)
Abstract: in embodiments herein, a surface finish (sf) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. in some embodiments, the sf may be electroless nickel-electroless palladium-immersion gold (enepig). in other embodiments, the sf may be immersion gold-electroless palladium-immersion gold (igepig). in other embodiments, the sf may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
20250219021. VERTICALLY EMBEDDED COMPONENTS PACKAGE SUBSTRATES (Intel)
Abstract: in embodiments herein, circuit components are embedded within a core layer of a substrate. the circuit components are vertically oriented within a cavity or hole of the core layer of the substrate, e.g., with conductive contacts on an edge of the component that is substantially orthogonal to a plane of the core layer. the edge that is substantially orthogonal to a plane of the core layer may be the longest edge of the component.
20250219028. DEEP TRENCH CAPACITORS MULTI-CORE INTEGRATED CIRCUIT DEVICE PACKAGE SUBSTRATES (Intel)
Abstract: an apparatus is provided which comprises: a substrate core comprising a first core layer bonded with a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and wherein the first circuit component comprises a deep trench capacitor, and one or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface. other embodiments are also disclosed and claimed.
20250219040. Technologies Components Embedded Substrate Core (Intel)
Abstract: technologies for components embedded in a substrate core are disclosed. in one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. the power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
20250219041. TECHNOLOGIES MEMORY POWER COMPONENTS EMBEDDED SUBSTRATE CORE (Intel)
Abstract: technologies for memory and power components embedded in a substrate core are disclosed. in one embodiment, memory components such as a high-bandwidth memory stack and power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. the components are stacked on top of each other, allowing for the stack of components to match the height of the substrate core, even when the height of the individual components is less than the height of the substrate core. configuring the memory and power components in this manner can provide mechanical stability to the power components and substrate core and provide close access to memory and power for a semiconductor die mounted on the circuit board.
Abstract: a device may include a plurality of carriers, wherein each carrier includes a plurality of communication processors, each communication processor disposed over or in a respective carrier of the plurality of carriers and configured to provide a wireless broadcasting communication channel, and a plurality of antennas, each antenna disposed on or in a respective carrier and coupled to a respective communication processor, wherein each antenna extends into a corner of the respective carrier, and wherein the antennas of each pair of adjacent carriers are positioned at a distance from each other at less than about 1 wavelength corresponding to the lowest operating frequency.
20250219349. HYBRID SILICON QUANTUM DOT LASERS (HSQDL) REDUCED THERMAL RESISTANCE (Intel)
Abstract: hybrid silicon quantum dot laser (hsqdl) structure including an optical waveguide of a first width, a mesa of a second width and a current channel of a third width that is smaller than the second width. in some examples, the third width is only slightly larger than the first width to narrowly confine electrical current directly over the optical waveguide while the third width is significantly larger than the first width to efficiently transport heat away from the optical gain medium. while the current channel has a low electrical resistivity, other regions of the mesa contributing to the third width have a higher electrical resistivity. in some examples, an implant process is practiced to increase electrical resistivity.
20250219581. OSCILLATOR ARRAY COUPLING THROUGH FERROELECTRIC CAPACITORS (Intel)
Abstract: an apparatus comprising a first electrical oscillator, a second electrical oscillator, at least one ferroelectric capacitor coupled between the first electrical oscillator and the second electrical oscillator, a ferroelectric capacitor of the at least one ferroelectric capacitor comprising a first terminal, a second terminal, and a ferroelectric material between the first terminal and the second terminal; and a detector coupled to the first electrical oscillator and second electrical oscillator, the detector to produce an output based on a state of the first electrical oscillator and the second electrical oscillator.
20250219643. HIGHLY SCALABLE ENTROPY SOURCE (Intel)
Abstract: an apparatus configured as an entropy source circuit includes a bistable circuit, a first latch circuit, a charge pump circuit, and an oscillator circuit. the bistable circuit generates random bits based on an input clock signal and a plurality of voltage adjustment signals. the first latch circuit is coupled to the bistable circuit and generates entropy bits based on the random bits. the charge pump circuit is coupled to the latch circuit and generates the plurality of voltage adjustment signals based on the entropy bits and a plurality of clock phases (e.g., a redistribute clock signal and a precharge clock signal). the entropy source circuit can be coupled in a ring topology with a plurality of other entropy source circuits, where the plurality of clock phases can be generated based on output clock signals received from at least one of the plurality of other entropy source circuits.
20250219739. RECONFIGURABLE DEFRAMER OPTICAL COMMUNICATIONS (Intel)
Abstract: a system includes a first chiplet that includes at least one demodulator for demodulating at least one received signal from a receiver to generate hard bits and soft information from the received signal and a second chiplet coupled to exchange information with the first chiplet. the second chiplet includes at least one correlator to detect a symbol pattern indicating frame boundaries of frames having a known frame symbol period length in an acquisition state and transitioning the first and second chiplets to a connected state in response to a threshold number of successful frame boundary detections. the at least one correlator uses soft bit representations to correlate and deduce the frame boundaries in a windowed mode using the known frame length and previous frame boundary information while in the connected state and transitions the first and second chiplets out of the connected state and back to the acquisition state in response to at least one unsuccessful frame boundary detection.
20250219740. COHERENT RECEPTION ON/OFF KEYING PULSE POSITION MODULATIONS (Intel)
Abstract: an optical receiver implements a method to provide a digital output of a received on-off keyed optical signal. the method includes receiving an on-off keyed optical signal via a coherent optical front-end receiver utilizing a locally mixed laser lo for a reference signal to perform quadrature detection of the optical signal to generate an electrical signal, performing symbol/slot timing recovery on the electrical signal using a timing error detector, performing carrier frequency and phase recovery on a symbol/slot signal to generate a frequency and phase recovered signal, and demodulating the frequency and phase recovered signal via a demodulation circuit to provide a digital output representative of the received on-off keyed optical signal.
20250219751. RATELESS CODING FEEDBACK SCHEME COMMUNICATION SYSTEMS (Intel)
Abstract: a device can include memory to store source packets and coded packets. the device can include processing circuitry to perform a first coding phase and a second coding phase. in the first coding phase, the processing circuitry can combine the source packets to generate a first set of coded packets, where a coded packet can be defined according to a degree, the degree being a count of the source packets used to generate the coded packet. in the second coding phase, the same source packets into a second set of coded packets, such that a total number of coded packets generated in the first encoding phase and in the second encoding phase is greater than a total number of source packets. in another aspects, broadcasters can receive feedback beacons and modify broadcast accordingly.
Abstract: an on-die key generator includes a pseudo-random number generator (prng) and a sampler. the pseudo-random number generator generates integers modulo a power-of-two number, based on an initial seed. the sampler uniformly maps the integers generated by the random number generator (rng) from the number space of 0â(2â1) to the ciphertext modulus space of 0â(qâ1) by randomly mapping the integers generated by the pseudo-random number generator that are greater than or equal to q to a value inside the range [0, qâ1] using additional random bits.
20250219861. PAGE-BASED REMOTE MEMORY ACCESS USING SYSTEM MEMORY INTERFACE NETWORK DEVICE (Intel)
Abstract: examples described herein and includes at least one processor and a direct memory access (dma) device. in some examples, the dma device is to: access a command from a memory region allocated to receive commands for execution by the dma device, wherein the command is to access content from a local memory device or remote memory node. in some examples, the dma device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. in some examples, the dma device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.
20250219926. TECHNOLOGIES PROTOCOL EXECUTION AGGREGATION CACHING (Intel)
Abstract: technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system. the aggregated status message identifies a success or failure of execution of instructions corresponding with the protocol message by the plurality of computing devices such that each computing device of the plurality of computing devices that failed is uniquely identified and the success of remaining computing devices is aggregated into a single success identifier.
Abstract: disclosed herein are devices, methods, and systems for encoding data packets for transmitting over at least two transmission paths, which may include a sub-6 ghz link and multiple high frequency band links. the system may divide an upper layer packet into a predefined number of equal-sized segments, encode the segments with linear packet network coding to generate a set of network coded packets, allocate for transmission to a destination node over two or more transmission paths subsets of the set of network coded packets to corresponding ones of the two or more transmission paths, and transmit to the destination node each subset of the subsets of network coded packets on its corresponding transmission path of the two or more transmission paths. the linear packet network coding may be optimized using a recursive method to allocate packets using decoding success probability and/or through a steepest decent or equalized distribution algorithm
20250219934. PITSTOP: FAULT HANDLING APPROACH DATA CENTER NETWORKS END-TO-END FLOW CONTROL (Intel)
Abstract: examples described herein relate to a forwarding element. in some examples, the forwarding element include circuitry that is to: based on detection of a faulty link in a path through forwarding elements to a destination device, direct a packet to a network interface device to cause the packet to traverse a second path to the destination device to bypass the faulty link to the destination device.
Abstract: techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. other embodiments are described and claimed.
20250220087. ACCESSING SERVICE INTERNET THINGS (Intel)
Abstract: methods, systems, and storage media for accessing one or more services provided by one or more detected internet of things (âiotâ) devices are described. in embodiments, a mobile device may detect a plurality of iot devices, obtain an identifier for each of the plurality of iot devices based on the detection, and obtain an indicator for each of the plurality of iot devices based at least in part on a corresponding one of the obtained identifiers, wherein each indicator may indicate a service type of a corresponding one of the plurality of iot devices. the mobile device may generate a notification that indicates a plurality of services available to the mobile device based on each of the obtained indicators. the mobile device may access a service of the plurality of services, wherein the access may include utilization of a set of the plurality of iot devices required to provide the service. other embodiments may be described and/or claimed.
20250220088. SERVICE REGISTRY FUNCTION DISCOVERING SERVICE INSTANCES (Intel)
Abstract: an apparatus and system of providing a service registry function (srf) and service discovery in a 6g system are described. registration procedures are provided for a service instance on a user equipment (ue) or in the 6g system to register to the srf with or without a service mesh. the srf provides a list of service instances based on criteria in service discovery inquiries from the ue or network function (nf) and notifies a subscribed party about a status change of a particular service instance. the service discovery enables the ue to discover a computing service instance in the 6g system by control plane service discovery to find a service orchestration and chaining function (socf) and user plane service discovery to find the computing service instance.
20250220403. Internet Things (Intel)
Abstract: the internet can be configured to provide communications to a large number of internet-of-things (iot) devices. an example non-transitory, machine readable medium comprises instructions that, when executed, direct a processor to: cause a device to connect to a network of a decentralized database, discover a namespace of a node of the decentralized database, create a shared database partition in response to being accepted by the node, advertise a service to the decentralized database; and route data of a service between a private database partition and the shared database partition
20250220582. TRANSMISSION TRIGGERING USING SEPARATE LOW-POWER WAKE-UP RECEIVER (Intel)
Abstract: various embodiments herein provide techniques related to a main receiver of a user equipment (ue) and a wake-up receiver (wur) of the ue. in the embodiments, the wur receives a low-power wake-up signal (lp-wus) from a base station. based on the lp-wus, the wur may be configured to wake-up the main receiver of the ue, wherein the ue identifies received configuration information including duty cycle parameters and detects the lp-wus based on the configuration information, and wherein the ue sets a state of the wake-up receiver based on an rrc state of the main receiver.
20250220675. TRANSMISSION UPLINK CONTROL INFORMATION (Intel)
Abstract: this disclosure describes systems, methods, and devices related to optimized uplink transmission. a device may receive a configuration of a first physical uplink control channel (pucch) resource and a set of second pucch resources associated with a first pucch resource. the device may transmit a first uplink control information (uci) part on the first pucch resource. the device may select a second pucch resource from the set of second pucch resources based on a payload size of a second uci part determined from the first uci part. the device may transmit the second uci part on the selected second pucch resource.
Abstract: various embodiments herein provide techniques related to a user equipment (ue). the ue may identify, by a long term evolution (lte) sidelink (sl) module that is to facilitate communication via a first sl channel of a first cellular network, a resource that is to be used for communication in the first sl channel by another ue; provide, by the lte sl module, information related to use of the resource to a new radio (nr) sl module that is to facilitate communication via a second sl channel of a second cellular network; and exclude, by the nr sl module based on the information related to use of the resource, the resource for communication via the second sl channel. other embodiments may be described and/or claimed.
20250220748. METHODS DEVICES RADIO COMMUNICATION NETWORKS (Intel)
Abstract: an apparatus of a communication device, the apparatus comprising a processor configured to: establish a first connection through a first radio frequency interface; establish a second connection through a second radio frequency interface, wherein the first connection is a non-secure connection and the second connection is a secure connection; determine a result representing whether data is routed for the first connection or the second connection; instruct the data to be transmitted with one of the first connection or the second connection based on the result.
20250220818. FLOW ENHANCED DUMMY STRUCTURE ENABLE CAPILLARY FLOW BASED SIDEWALL FILLING (Intel)
Abstract: embodiments disclosed herein include an apparatus with a component embedded in a core. apparatuses disclosed herein may comprise a first component with a first surface and a second surface opposite from the first surface, where a pad is provided on the first surface. in an embodiment, a layer is over the second surface of the first component, and a second component is over the layer. in an embodiment, the second component comprises a hole that passes through at least a partial thickness of the second component.
20250220819. COMPONENT EMBEDDED MOLD MATERIAL MITIGATING THICKNESS MISMATCH CORE (Intel)
Abstract: embodiments disclosed herein include passive electrical components with thickness modifications in order to improve embedding processes. in an embodiment, such an apparatus comprises a substrate with a first width, where the substrate comprises a first surface, a second surface opposite from the first surface, and sidewall surfaces coupling the first surface to the second surface. in an embodiment, a layer with a second width that is greater than the first width contacts the substrate and covers the sidewall surfaces and the first surface of the substrate.
20250220857. VAPOR COMPRESSION ASSISTED LIQUID COOLING SYSTEM ELECTRONIC COMPONENTS (Intel)
Abstract: disclosed herein are devices, methods, and systems for cooling an electronic component. the cooling device includes a liquid cooling loop with a heat exchanger, wherein the liquid cooling loop thermally conductively connects to the electronic component. the cooling device also includes a vapor compression cooling loop with a compressor and an expansion nozzle. the cooling device also includes an intermediate heat exchanger between the liquid cooling loop and the vapor compression cooling loop for exchanging heat between the liquid cooling loop and the vapor compression cooling loop. the cooling device also includes a controller configured to selectively activate the vapor compression cooling loop based on a power consumption of the electronic component.
Abstract: integrated circuit structures having varied epitaxial source or drain structures and device types are described. in an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires, each of the second plurality of horizontally stacked nanowires having a lateral width less than a lateral width of each of the first plurality of horizontally stacked nanowires. first epitaxial source or drain structures are at ends of the first plurality of horizontally stacked nanowires, each of the first epitaxial source or drain structures having a maximum lateral width. second epitaxial source or drain structure are at ends of the second plurality of horizontally stacked nanowires, each of the second epitaxial source or drain structures having a maximum lateral width greater than the maximum lateral width of each of the first epitaxial source or drain structures.
Abstract: apparatuses, systems, and techniques related to ferroelectric material systems including hafnium oxide-based ferroelectric layers are described. a ferroelectric material system includes an oxide layer on the hafnium oxide-based ferroelectric layer, and an oxygen migration mitigation layer on the oxide layer. the oxygen migration mitigation layer is niobium nitride, tantalum nitride, ruthenium oxide, molybdenum, tungsten, ruthenium or palladium, and a metallic electrode is formed on the oxygen migration mitigation layer.
20250220925. THREE-DIMENSIONAL MEMORY ARCHITECTURES HYBRID BONDING (Intel)
Abstract: three-dimensional (3d) memory architectures with hybrid bonding and methods for making same. methods and apparatus employ ultra-high density (defined herein as sub 1 micron pitch) hybrid bond interface (hbi) stacking die/chiplets at the memory bank level. various configurations for distributing the memory bank and the peripheral logic between a bottom die and a top die are described, with application to further die stacking. provided apparatus may also implement dedicated vias for power delivery from a principle bottom die to the top die.
Abstract: apparatuses, systems, and techniques related to ferroelectric material systems including hafnium oxide-based ferroelectric layers are described. a ferroelectric material system includes a hafnium oxide-based ferroelectric layer and a defect compensation material on the hafnium oxide-based ferroelectric layer. the defect compensation material is an oxide having a stronger bound dissociation energy relative to the hafnium oxide-based ferroelectric layer to compensate for oxygen defects formed in the hafnium oxide-based ferroelectric layer.
20250220944. METHOD CONTROLLING METAL GATE HEIGHT SELECTIVE SPACER FORMATION (Intel)
Abstract: integrated circuit (ic) devices with non-planar transistors may be formed from a material stack having a sacrificial layer between one or more mask material layers and a top surface of a channel material. an ic device may include a non-planar transistor with a gate spacer layer having portions with a same or consistent composition, both over an upper surface of the channel material and under a lower surface of the channel material. the gate spacer layer may have a different composition than a gate endcap spacer layer.
20250220950. TRANSISTORS ASYMMETRIC SOURCE DRAIN CONTACTS (Intel)
Abstract: semiconductor devices and systems with asymmetric source and drain contacts, and methods of forming the same, are disclosed herein. in one example, a semiconductor device includes a source, a drain, a source contact, a drain contact, a channel, and a gate. the source contact is coupled to the source and the drain contact is coupled to the drain, and the source contact and the drain contact are asymmetric. the source and the drain are coupled via the channel, and the gate is coupled to the channel.
20250220952. BACKSIDE CONTACT STRUCTURES FABRICATION METAL BOTH SIDES DEVICES (Intel)
Abstract: an apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. a method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
20250220958. SOURCE/DRAIN CONTACT TRENCH DIELECTRIC LINER CONTACT METAL (Intel)
Abstract: an integrated circuit device comprising at least one first layer at a bottom of a trench, the at least one layer connecting to a source/drain region of a transistor, the at least one layer comprising metal; a second layer on the at least one first layer, the second layer comprising metal; and a third layer on the at least one first layer and within the trench, the third layer comprising a dielectric material.
20250220959. FRONT SIDE BACKSIDE SOURCE OR DRAIN CONTACTS (Intel)
Abstract: an integrated circuit structure includes a device layer including a plurality of devices. the plurality of devices includes (i) a plurality of source and drain regions, (ii) a plurality of gate stacks, and (iii) a plurality of gate spacers, each gate spacer separating a corresponding source or drain region from a corresponding gate stack, the gate spacers comprising a first dielectric material. a first source or drain contact is coupled to a frontside of a first source or drain region of the plurality of source or drain regions. a second dielectric material is coupled to a backside of the first source or drain region. a second source or drain contact is coupled to a backside of a second source or drain region of the plurality of source or drain regions. in an example, the first dielectric material and the second dielectric material comprise the same elemental constituents.
Abstract: integrated circuit structures having uniform grid metal gate and trench contact cut with recesses for via landing are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires. a gate electrode is over the vertical stack of horizontal nanowires. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. a first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. a second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.
Abstract: integrated circuit structures having links for uniform grid metal gate and trench contact cut are described. for example, an integrated circuit structure includes a gate electrode over a vertical stack of horizontal nanowires or a fin. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. first and second parallel dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. the second dielectric cut plug has a recess laterally adjacent to the conductive trench contact and exposing a side of the conductive trench contact. a conductive link is in the recess of the second dielectric cut plug structure.
Abstract: integrated circuit structures having links for uniform grid metal gate and trench contact cut are described. for example, an integrated circuit structure includes a gate electrode over a vertical stack of horizontal nanowires or a fin. a conductive trench contact is adjacent to the gate electrode, with a dielectric sidewall spacer there between. first and second parallel dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. a first conductive link is in a recess of the first dielectric cut plug structure and is in contact with a side of the gate electrode. a second conductive link is in a recess of the second dielectric cut plug structure and is in contact with a side of the conductive trench contact.
20250220969. GATE-ALL-AROUND DEVICES DIFFERENT GATE LENGTHS (Intel)
Abstract: techniques are provided herein to form semiconductor devices having different gate lengths on the same die. in an example, any number of first semiconductor devices includes first gate structures around first semiconductor regions and any number of second semiconductor devices include second gate structures around second semiconductor regions. the first gate structures have a first gate length around the first semiconductor regions and the second gate structures have a second gate length around the second semiconductor regions with the second gate length being greater than the first gate length. an upper thickness of each the first and second gate structures may be the same, despite the gate length diversity. the first semiconductor devices include first inner spacer structures around ends of the first semiconductor regions that have a greater lateral thickness compared to second inner spacer structures around ends of the second semiconductor regions of the second semiconductor devices.
20250220978. INTEGRATED CIRCUIT STRUCTURE ASYMMETRIC EPITAXIAL SOURCE OR DRAIN ARRANGEMENTS (Intel)
Abstract: integrated circuit structures having asymmetric epitaxial source or drain arrangements are described. an integrated circuit structure includes a gate stack over a plurality of horizontally stacked nanowires. a first epitaxial source or drain structure is at a first end of the plurality of horizontally stacked nanowires. a first gate spacer laterally between the gate stack and the first epitaxial source or drain structure. a second epitaxial source or drain structure is at a second end of the plurality of horizontally stacked nanowires. a second gate spacer is laterally between the gate stack and the first epitaxial source or drain structure. the first gate spacer has a width less than the second gate spacer or the tips of the first epitaxial source or drain structure have a greater lateral width than the tips of the second epitaxial source or drain structure by an amount of 10% or greater, or both.
20250220986. AIRGAP SPACER WRAPPED AROUND CONTACT (Intel)
Abstract: techniques are provided to form semiconductor devices that include an epitaxial contact with an airgap spacer surrounding a portion of the contact. accordingly, the airgap spacer is between the contact and an adjacent gate structure and is between the contact and an adjacent dielectric structure. a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region) that extends from a first source or drain region to a second source or drain region. a dielectric structure may extend through an entire thickness of the gate structure and along the first direction to also be adjacent to the first and second source or drain regions. conductive conducts are formed on one or both of the first source or drain region and the second source or drain region. an airgap spacer wraps around the entire perimeter of at least one of the conductive contacts.
20250220990. GATE CUT PLUG THIN HERMETIC LINER LOW-K FILL REDUCED CAPACITANCE OXIDATION (Intel)
Abstract: integrated circuit (ic) device isolation structures between transistor gates. an ic device may include an electrically insulating structure between metal gates of adjacent transistors, and the insulating structure may include a dielectric liner around a different dielectric fill material and on sidewalls of the adjacent metal gates. the dielectric liner may be much thinner than the dielectric fill material. a metal via may be through, and in contact with, the dielectric fill material. the adjacent transistors and metal gates may be between frontside and backside interconnect structures, and the metal via may extend between, and couple, the interconnect structures.
20250220991. INTEGRATED CIRCUIT STRUCTURE DIRECT BACKSIDE SOURCE OR DRAIN CONTACT (Intel)
Abstract: integrated circuit structures having direct backside source or drain contacts are described. in an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. a first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the first epitaxial source or drain structure without contacting the first gate stack or the second gate stack. a second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin.
20250220994. BACKSIDE EPITAXIAL GROWTH IMPROVED CONTACT AREA (Intel)
Abstract: techniques are provided to form an integrated circuit having backside epaxially grown source or drain regions in addition to the frontside source or drain regions to reduce backside contact resistance. a semiconductor device includes a gate structure around or otherwise on a semiconductor region. the gate structure includes a gate dielectric and a gate electrode. the substrate beneath the semiconductor device may be removed from the backside to expose a subfin region beneath the semiconductor region. the subfin region may be removed using a backside etch to open a backside recess that exposes a bottom surface of a given frontside source or drain region. a backside source or drain region may be grown on a bottom surface of the given frontside source or drain region and remain within the backside recess or extend out of the backside recess.
20250221017. HV TRANSISTORS & RESISTORS STACKED TRANSISTOR ARCHITECTURES (Intel)
Abstract: a material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into both a low voltage transistor structure and a high voltage transistor structure. within the low voltage transistor structure, a first of two semiconductor material layers may be replaced with a gate stack while the high voltage transistor structure may retain both of two semiconductor material layers. the material stack may also be fabricated into both a transistor structure and a resistor structure. within the transistor structure, a first of two semiconductor material layers may be replaced with a gate stack while the resistor structure may retain both of two semiconductor material layers.
Abstract: integrated circuit structures having uniform grid metal gate and trench contact cut are described. for example, an integrated circuit structure includes a first and second vertical stacks of horizontal nanowires or fins. a first gate structure is over the first vertical stack of horizontal nanowires or fin, and a second gate structure is over the second vertical stack of horizontal nanowires or fin, the second gate structure having voltage threshold (vt) different than a vt of the first gate structure. a conductive trench contact is adjacent to the first gate structure and the second gate structure. a dielectric sidewall spacer is between the first gate structure and the conductive trench contact, and between the second gate structure and the conductive trench contact. a dielectric cut plug structure is extending between the first gate structure and the second gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.
20250221020. DOUBLE-SIDED DEVICE CONTACTS THROUGH VIAS PERFORMANCE LAYOUT BENEFITS (Intel)
Abstract: an integrated circuit (ic) device includes transistors between front- and back-side interconnect layers and having source and/or drain regions with front- and back-side contacts. the transistors may be between isolation structures on a same pitch as the transistor gates, sources, and drains. via structures adjacent to the transistors couple between the front- and back-side interconnect layers. the transistors and isolation and via structures may be utilized in various logic cells. transistors having front- and back-side source and/or drain contacts may include vias through or alongside the source and/or drain regions.
20250221023. INTEGRATED CIRCUIT STRUCTURE BACKSIDE CONTACT EXTENSION (Intel)
Abstract: integrated circuit structures having backside contact extensions are described. in an example, a structure includes a first and second pluralities of horizontally stacked nanowires or fins. first and second gate stacks are over the first and second pluralities of horizontally stacked nanowires or fins. an epitaxial source or drain structure is between the first and second pluralities of horizontally stacked nanowires or fin. a dielectric structure is over the first gate stack, over the second gate stack, and over the epitaxial source or drain structure, the dielectric structure having an opening over the epitaxial source or drain. a conductive structure is in the opening in the dielectric structure and on the epitaxial source or drain structure, the conductive structure having a top surface below a top of the opening. a conductive extension is on the conductive structure, the conductive extension in and protruding above the opening in the dielectric structure.
20250221040. INTEGRATED CIRCUIT STRUCTURE FRONT-SIDE-CUT BACKSIDE SOURCE OR DRAIN CONTACT (Intel)
Abstract: integrated circuit structures having front-side-cut backside source or drain contacts are described. in an example, an integrated circuit structure includes a first gate stack over a first plurality of horizontally stacked nanowires or fin, and a second gate stack over a second plurality of horizontally stacked nanowires or fin. a first epitaxial source or drain structure is at an end of the first plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a backside contact structure thereon. a second epitaxial source or drain structure is at an end of the second plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. a dielectric gate cut plug is laterally between and in contact with the backside dielectric structure and the backside contact structure.
20250221041. INTEGRATED CIRCUIT STRUCTURE FRONT-SIDE-GUIDED BACKSIDE SOURCE OR DRAIN CONTACT (Intel)
Abstract: integrated circuit structures having front-side-guided backside source or drain contacts are described. in an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. a first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. a second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. a dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.
Abstract: magnetoelectric spin-orbit (meso) devices, integrated circuit devices and systems with meso devices, and methods of forming the same, are disclosed herein. in one embodiment, a semiconductor device includes: a first layer that includes a magnetoelectric material; one or more second layers over the first layer, where the second layer(s) include one or more ferromagnetic materials; a third layer over the second layer(s), where the third layer includes an antiferromagnetic material; and a fourth layer over the third layer, where the fourth layer includes at least one of a metal, a topological insulator, or a two-dimensional (2d) semiconductor material.