Intel Corporation patent applications on 2025-06-12
Patent Applications by Intel Corporation on June 12th, 2025
Intel Corporation: 33 patent applications
Intel Corporation has applied for patents in the areas of H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application), 2), B08B1/30 (by movement of cleaning members over a surface, 1), H01Q1/2283 ({mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}, 1), H10D84/017 (No explanation available, 1), H10D64/254 (No explanation available, 1), H10D64/017 (No explanation available, 1), H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass, 1), H04W74/0816 (with collision avoidance, 1), H04W48/16 (Discovering, processing access restriction or access information, 1), H04R1/345 ({for loudspeakers}, 1)
With keywords such as: configured, frame, various, assembly, having, provide, cleaning, mounting, aspects, linked in patent application abstracts.
Top Inventors:
- Diego DELFIN MANRIQUEZ of Gilbert AZ US (1 patents)
- Todd COONS of Gilbert AZ US (1 patents)
- Kehai ZHANG of Chandler AZ US (1 patents)
- Michael A. SCHROEDER of Chandler AZ US (1 patents)
- Jensen STENBERG of Phoenix AZ US (1 patents)
Patent Applications by Intel Corporation
20250187041. CLEANING ASSEMBLY, CLEANING SYSTEM METHOD (Intel)
Abstract: various aspects may provide a cleaning assembly having a mounting frame configured to be linked with a connector-holding arrangement. the cleaning assembly may further include a displaceable member configured to support a cleaning element thereon. the displaceable member may be operatively coupled to the mounting frame in a manner so as to be displaceable relative to the mounting frame, along a movement axis, between a first position and a second position of the displaceable member. in the first position of the displaceable member, the displaceable member may be apart from a cleaning-axis of the cleaning assembly. the cleaning-axis may be non-parallel to the movement axis and, with the mounting frame linked with the connector-holding arrangement, the cleaning-axis may be aligned with a connector-alignment-axis of the connector-holding arrangement. in the second position of the displaceable member, the displaceable member may intersect the cleaning-axis.
20250187181. ENERGY EFFICIENT ROBOTIC ARM (Intel)
Abstract: various aspects of techniques, systems, and use cases may be used for operating, controlling, programming, or configuring an energy efficient robotic arm. an example technique may include identifying a planned trajectory for a robotic arm, selecting a candidate joint of the robotic arm to lock, and recomputing the planned trajectory to determine a joint-locked trajectory while the candidate joint is locked. the example technique may include outputting a control signal to lock the candidate joint and causing the robotic arm to use the joint-locked trajectory.
20250190223. PROCESSING UNIT, SOFTWARE MODULE, METHODS PROGRAM CODES (Intel)
Abstract: a device is provided. the device includes one or more interfaces configured to communicate with a plurality of random-access memories (ram) and processing circuitry configured to control the one or more interfaces and to transmit a load message to each ram of the plurality of ram and determine a status of each ram of the plurality of ram.
20250190239. METHOD APPARATUS VIRTUAL MACHINE PERFORMANCE MEASUREMENT (Intel)
Abstract: methods, apparatus, and computer programs are disclosed to support virtual machine performance measurement. in one embodiment, a method includes, responsive to a virtual machine entry to a virtual processing unit of a processor, writing a first and a second count value corresponding to the virtual processing unit to a first and second counter, respectively; incrementing the first counter counts based on the first count value at a fixed frequency and incrementing the second counter counts based on the second count value in proportion of architectural event occurrence of the virtual processing unit; and responsive to a virtual machine exit from the virtual processing unit, reading a resulting first and second count value from the first and second counters respectively to determine a measure of the performance of the virtual processing unit.
20250190277. APPARATUS METHOD MANAGEABLE FRAGMENTED ACCELERATION STRUCTURES (Intel)
Abstract: apparatus and method for manageable fragmented acceleration structures. for example, one embodiment of an apparatus comprises: acceleration structure construction logic to build an acceleration structure (as) including a multi-level linkage hierarchy with different types of as fragments, the different types of as fragments including a first type of as fragments with leaves, a second type of as fragments including as linkages, and a third type of as fragment including both leaves and as linkages, wherein to construct an as fragment, the acceleration structure construction logic is to: evaluate a plurality of primitive references, determine whether each primitive reference indicates a primitive or an as fragment, and if the primitive reference indicates an as fragment, then encode a pointer or offset directly or indirectly into a bounding volume hierarchy (bvh) of the as fragment; and traversal hardware logic to traverse a ray through the as.
20250190360. OS-TRANSPARENT MEMORY DECOMPRESSION HARDWARE ACCELERATION (Intel)
Abstract: methods and apparatus for operating system (os)-transparent memory decompression with hardware acceleration. a physical address space for system memory is partitioned into compressed and uncompressed partitions. a core issues a memory read request and on-chip l1, l2, and a last level cache (llc) are checked, with misses leading to page table lookups to determine where in system memory the requested data are stored. when stored in the compressed partition, a compressed page table is searched to find the location of the compressed form of the data on a memory device. the compressed data are read from the memory device, decompressed using hardware acceleration and returned to the requesting core without writing the data to the uncompressed partition. under one approach, a compressed page containing the requested data is decompressed and written to the llc. when data (e.g., cache lines) in the decompressed page in the llc are written to, the decompressed page is evicted from the llc and written to the uncompressed partition.
20250190370. REDUCED LATENCY LOW-POWER STATE EXIT (Intel)
Abstract: in some embodiments, low-power states, where exit code is stored in a vulnerable memory and should be crypto verified, may be enhanced by verifying the code before entering the low-power state and storing it in a write-lockable memory so that it may be executed when coming out of the low-power state without having to crypto verify it.
20250190523. LUT-FREE HARDWARE BASED SOFTMAX ACCELERATOR (Intel)
Abstract: softmax operation is one part of a deep neural network (dnn). because computing softmax is complex and time-consuming, the softmax operation can limit the overall execution latency of the dnn. to address this issue, an in-line data path is added to pass output data from a matrix-to-matrix multiplication core to a hardware softmax accelerator. during a denominator phase of the softmax operation, the softmax accelerator can operate in-line to produce a denominator value using output values generated by the matrix-to-matrix multiplication core and received over the in-line data path. during a numerator phase of the softmax operation, the softmax accelerator can calculate softmax outputs using output values generated by the matrix-to-matrix multiplication core and retrieved from a memory. in other words, the softmax accelerator can produce partial results while the matrix-to-matrix multiplication is in-flight to cut down overall latency and reduce memory transactions.
20250191118. SEMANTIC KNOWLEDGE-BASED TEXTURE PREDICTION ENHANCED IMAGE RESTORATION (Intel)
Abstract: systems and methods for determining a texture map for a high resolution image based on a downscaled low resolution version of the image. a texture map is used in image signal processing and image restoration systems to provide a location-specific indication of whether a particular area of an image includes high texture, low texture, edges, or flat regions. using a low resolution version of the image, semantic cues are integrated with texture information to enable efficient, accurate, and cost-effective texture predictions and generate a texture classification map. the texture classification map based on the low resolution image is upscaled to a high resolution texture classification map. the texture classification map information can then be used to determine a selected filter to apply to each pixel and/or area in the high resolution image. the system provides spatially consistent decisions and improved noise robustness in texture to facilitate accurate image restoration.
20250191142. RADIOMETRIC COMPENSATION TEMPORAL NOISE REDUCTION VIDEO (Intel)
Abstract: systems and methods for providing a temporal noise reducer (tnr) architecture that improves tnr performance by adjusting for lighting differences between image frames. temporal noise reduction is a core feature of a video processing pipeline, where tnr can be used to decrease noise in video streams. some tnrs compensate for the motion of objects between frames, but lighting changes can also lead to additional noise. as an object's position moves from frame to frame, the lighting of the object may change. a lightweight tone-mapping and color-correction operator is added to the tnr feedback loop, matching the radiometric properties of a tnr reference frame to the radiometric properties of the current frame to compensate for radiometric differences, thereby increasing the effectiveness of tnr in handling incremental lighting changes and speeding up its response to abrupt lighting changes.
20250191998. ENHANCED BASE DIE HEAT PATH USING THROUGH-SILICON VIAS (Intel)
Abstract: embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (tsvs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. in embodiments, the first die may be referred to as a base die. embodiments may include thermal blocks in the form of dummy dies that include tsvs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
Abstract: alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. in an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. the substrate has a perimeter. a metallization structure is disposed on the lower insulating layer. the metallization structure includes conductive routing disposed in a dielectric material stack. first and second pluralities of conductive pads are disposed in a plane above the metallization structure. conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. an upper insulating layer is disposed on the first and second pluralities of conductive pads. the upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.
20250192032. METHOD ENABLE LOGIC FOCUSED ION BEAM CIRCUIT EDIT UPPERMOST ROUTING LAYERS (Intel)
Abstract: according to various examples, a semiconductor device for backside power delivery is described. the semiconductor device may include a device layer including an integrated circuit, wherein the device layer is between a top metal layer and a bottom metal layer. the semiconductor device may also include a focused-ion beam access point on the top metal layer. the semiconductor device may also include one or more tie cells connected to the integrated circuit of the device layer. the semiconductor device may also include one or more functional cells connected to the one or more tie cells, wherein the one or more tie cells and one or more function cells provide an electrical route on the top metal layer to the focused-ion beam access point.
20250192059. EMBEDDED BRIDGE THROUGH SILICON VIA BONDING ARCHITECTURES (Intel)
Abstract: embodiments disclosed herein include bridge structures for package substrates. in an embodiment, a package substrate comprises a substrate that is a dielectric material. in an embodiment, a cavity is formed into the substrate. a first pad is on a bottom surface of the cavity, and a die is at least partially in the cavity. in an embodiment, a via passes through at least a portion of a thickness of the die, and a second pad is on the die. in an embodiment, the second pad directly contacts the first pad, and the first pad is the only electrically conductive structure between the via and the second pad.
20250192069. MICROELECTRONIC ASSEMBLIES PRE-SINGULATION EDGE FEATURES GLASS CORES (Intel)
Abstract: various techniques for alleviating crack formation and propagation in glass, and related devices and methods, are disclosed. the techniques are based on providing various edge features before singulation of a glass panel into individual glass units. in one aspect, an edge feature may be an opening in an edge region of a glass core, the opening extending from one of the faces of the glass core towards the opposite face of the glass core and comprising a fill material such as an insulator material, a polymer, or a conductive material. in another aspect, an edge feature may be an anchor comprising a first pad over one of the faces of a glass core, a second pad over the opposite face of the glass core, and a pin, wherein the pin is attached to the first pad and extends from the first pad into the glass core.
20250192070. MICROELECTRONIC ASSEMBLIES POST-SINGULATION EDGE FEATURES GLASS CORES (Intel)
Abstract: various techniques for alleviating crack formation and propagation in glass, and related devices and methods, are disclosed. the techniques are based on providing various edge features during or after singulation of a glass panel into individual glass units. in one aspect, a microelectronic assembly includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face, and further includes a protection coating on the edge. in another aspect, a microelectronic assembly includes a glass core as in the first aspect and further includes a frame around the edge. in yet another aspect, a microelectronic assembly includes a glass core with edges that have undergone thermal and/or chemical treatment.
20250192096. SELF-ASSEMBLY METHOD EQUIPMENT (Intel)
Abstract: a system that includes a self-assembly module and a bonding module. the self-assembly module has a liquid dispensing unit, with an applicator and a reservoir for a liquid, that dispenses the liquid onto a wafer, a wafer support, an environmental control unit, a die and wafer transport mechanism, and a processor. a method for performing the hybrid bonding includes providing a wafer, patterning the wafer to form a hydrophobic surface with a plurality of hydrophilic regions, disposing the wafer on the wafer support in the self-assembly module of the hybrid bonding system, dispensing the liquid simultaneously or in batches on the plurality of hydrophilic regions on the wafer, positioning dies on the plurality of hydrophilic regions on the wafer, controlling the humidity and bonding the dies to the wafer using a hybrid bonding process.
20250192101. NO MOLD SHELF PACKAGE DESIGN PROCESS FLOW ADVANCED PACKAGE ARCHITECTURES (Intel)
Abstract: embodiments include semiconductor packages and a method to form such semiconductor packages. a semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. the encapsulation layer surrounds the dies. the semiconductor package also includes a plurality of dummy silicon regions on the substrate. the dummy silicon regions surround the dies and encapsulation layer. the plurality of dummy silicon regions are positioned on two or more edges of the substrate. the dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. the dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. the materials have a thermal conductivity of approximately 120 w/mk or greater, or is equal to or greater than the thermal conductivity of silicon. an underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
20250192418. CHIP-TO-CHIP WAVEGUIDE CONTACTLESS CHIP-TO-CHIP COMMUNICATION (Intel)
Abstract: a wireless chip-to-chip device includes a first semiconductor substrate comprising a first antenna, configured to emit a radiofrequency signal; a second semiconductor substrate comprising a second antenna and configured to receive the radiofrequency signal; and a waveguide, positioned between the first semiconductor substrate and the second semiconductor substrate.
20250192754. LOW-POWER SINGLE-PHASE CLOCKED FLIP-FLOP (Intel)
Abstract: embodiments herein relate to a flip-flop circuit which uses a single clock signal for both the primary and secondary latches with either a “0” or a “1” being used to write into the primary latch and either a “1” or a “0,” respectively, being used to write into the secondary latch. the flip-flop can retain the data as long as the power supply is available. additionally, the flip-flop conserves power by disconnecting one or more paths to power or ground automatically based upon the data that is being stored, thus reducing the leakage current during a storage mode of operation.
20250192902. PLATFORM INTERFERENCE MITIGATION WIRELESS COMMUNICATIONS (Intel)
Abstract: disclosed herein are devices, methods, and systems for mitigating platform-based interference of wireless communications. the platform interference mitigation system may determine a platform-based wireless interference characteristic based on an operational setting of a computing platform, determine an interference mitigation parameter based on the platform-based wireless interference characteristic, and control a wireless communication interface of the computing platform based on the interference mitigation parameter. such platform-based interference mitigation allows for optimizing the computing platform operations as well as the wireless communication interface.
Abstract: this disclosure describes systems, methods, and devices related to 60 ghz operation. a device may utilize a legacy baseband data for a generation of a plurality of orthogonal frequency-division multiplexing (ofdm) symbols for a 60 ghz communication. the device may select a fixed number of subcarriers independently of bandwidth selection. the device may select a subcarriers spacing based on a bandwidth for the 60 ghz communication. the device may generate the plurality of ofdm symbols using an upclocking mechanism based on the bandwidth for the 60 ghz communication. the device may cause to send a plurality of ofdm symbols to a station device.
20250192974. CLOCK DISTRIBUTION USING RESONANT TRANSMISSION LINE (Intel)
Abstract: embodiments herein relate to a clock distribution network. in one aspect, the network includes a resonant transmission line-based architecture which includes a single inductive-capacitance (lc) termination along the distribution and an additional capacitive termination at the end of the distribution to independently tune the primary and secondary resonance frequencies of the network and perform 3rd-harmonic filtering. the lc termination can include a coil inductor or a short-circuited termination line with parallel conductors to provide an inductance.
20250193101. LOCAL PROTOCOL DATA UNIT (PDU) SESSION ANCHOR (PSA) SELECTION BASED N6 DELAY (Intel)
Abstract: various embodiments herein relate to a session management function (smf). the smf may be configured to identify, in a notification received from a local protocol data unit session anchor (psa), an indication of a transmission delay between the local psa and an edge application server (eas) via an n6 interface. the smf may then be configured to establish the local psa in a local psa insertion procedure based on the transmission delay. other embodiments may be described and/or claimed.
20250193295. TECHNOLOGIES DYNAMIC ACCELERATOR SELECTION (Intel)
Abstract: technologies for dynamic accelerator selection include a compute sled. the compute sled includes a network interface controller to communicate with a remote accelerator of an accelerator sled over a network, where the network interface controller includes a local accelerator and a compute engine. the compute engine is to obtain network telemetry data indicative of a level of bandwidth saturation of the network. the compute engine is also to determine whether to accelerate a function managed by the compute sled. the compute engine is further to determine, in response to a determination to accelerate the function, whether to offload the function to the remote accelerator of the accelerator sled based on the telemetry data. also the compute engine is to assign, in response a determination not to offload the function to the remote accelerator, the function to the local accelerator of the network interface controller.
20250193584. ELECTRONIC DEVICES CONFIGURABLE AUDIO DUCTS (Intel)
Abstract: disclosed herein are example systems, apparatus, articles of manufacture, and methods for configuring audio ducts of electronic devices. an example electronic device includes a chassis, a speaker, an audio duct formed on an edge of the chassis, and a deployable door movable between a first position adjacent the chassis and covering the audio duct and a second position exposing the audio duct.
20250193779. METHODS DEVICES RADIO COMMUNICATIONS (Intel)
Abstract: a circuit arrangement includes a preprocessing circuit configured to obtain context information related to a user location, a learning circuit configured to determine a predicted user movement based on context information related to a user location to obtain a predicted route and to determine predicted radio conditions along the predicted route, and a decision circuit configured to, based on the predicted radio conditions, identify one or more first areas expected to have a first type of radio conditions and one or more second areas expected to have a second type of radio conditions different from the first type of radio conditions and to control radio activity while traveling on the predicted route according to the one or more first areas and the one or more second areas.
20250193931. ENHANCED WI-FI ULTRA-LOW LATENCY OPERATIONS (Intel)
Abstract: this disclosure describes systems, methods, and devices related to performing wi-fi low-latency operations. a multi-link device (mld) may generate a first physical layer (phy) protocol data unit (ppdu); transmit, using a first station device of the mld, the first ppdu during a transmission opportunity (txop) for the first station device of the mld and a second station device of a second mld; identify a frame received by the first station device after transmission of the first ppdu indicating a request for the second station device or a third station device to transmit time-sensitive data to the first station device; identify time-sensitive data received by the first station device after transmission of the first ppdu; transmit, using the first station device, an acknowledgement indicative of receipt of the time-sensitive data by the first station device; generate the second ppdu; and transmit, using the first station device, the second ppdu.
20250194109. METHODS ARCHITECTURES HYBRID SOLDER SOLDERLESS DIE STACKING (Intel)
Abstract: methods and architectures for hybrid solder and solderless die stacking. devices include a semiconductor die that is solderless bonded (using hybrid bonding interconnect (hbi) technology) at a bottom surface to a base die. the semiconductor die includes a region with through silicon vias (tsvs) exposed at an upper surface. the semiconductor die and the tsvs are configured to have a solder-attach component, such as a dram or high bandwidth memory (hbm), attached thereto. the solder-attach component is stacked on the semiconductor die and soldered to the semiconductor die at the tsvs.
20250194201. TRENCH CONTACT STRUCTURES ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION (Intel)
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a fin. a gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. a gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. first and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. first and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a u-shaped metal layer and a t-shaped metal layer on and over the entirety of the u-shaped metal layer.
20250194211. CONDUCTIVE VIA FRONT-SIDE BACK-SIDE CONNECTIONS SOURCE OR DRAIN REGION (Intel)
Abstract: a fabrication method and associated integrated circuit (ic) structures and devices that include a conductive via with front-side and back-side connections with an s/d region are described herein. in one example, an ic structure includes a conductive via extending between a first layer and a second layer and an s/d region of a transistor between the first layer and the second layer, where the s/d region includes a first semiconductor material and a second semiconductor material. in one such example, the second semiconductor material may be epitaxially grown on the first semiconductor material of the s/d region from a back side of the ic structure. conductive elements in layers over and under the conductive via may couple the conductive via with the s/d region from both the front-side and back-side s/d contact structures.
20250194223. UNIAXIAL DUAL STRAIN RIBBONIZED CHANNEL (Intel)
Abstract: an integrated circuit structure includes laterally adjacent first and second devices. the first device includes (i) a first source or drain region having a first plurality of portions, (ii) a first plurality of bodies, each body of the first plurality of bodies laterally extending from a corresponding one of the first plurality of portions, and (iii) a first source or drain contact including a first conductive material and coupled to the first plurality of portions. the second device includes (i) a second source or drain region having a second plurality of portions, (ii) a second plurality of bodies, each body of the second plurality of bodies laterally extending from a corresponding one of the second plurality of portions, and (iii) a second source or drain contact coupled to the second plurality of portions and including a second conductive material elementally different from the first conductive material.
20250194235. FIN END PLUG STRUCTURES ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION (Intel)
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. a gate structure is over the fin and is spaced apart from the first isolation structure along the direction. a second isolation structure is over a second end of the fin, the second end opposite the first end. the second isolation structure is spaced apart from the gate structure. the first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. the recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.