Intel Corporation patent applications on 2025-06-05
Patent Applications by Intel Corporation on June 5th, 2025
Intel Corporation: 28 patent applications
Intel Corporation has applied for patents in the areas of H01L23/5381 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({ takes precedence; manufacture or treatment } ; mountings per se ; {materials }), 2), B23K3/0638 (SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM (making metal-coated products by extruding metal ; building up linings or coverings by casting ; casting by dipping ; manufacture of composite layers by sintering metal powder ; arrangements on machine tools for copying or controlling ; covering metals or covering materials with metals, not otherwise provided for ; burners ), 1), H04L5/0053 ({Allocation of signaling, i.e. of overhead other than pilot signals}, 1), H10D62/121 (No explanation available, 1), H04W74/0858 ({collision detection}, 1), H04W72/0457 (Wireless resource allocation, 1), H04W72/0453 (Resources in frequency domain, e.g. a carrier in FDMA, 1), H04W72/0446 (Resources in time domain, e.g. slots or frames, 1), H04W4/02 (WIRELESS COMMUNICATION NETWORKS (broadcast communication ; communication systems using wireless links for non-selective communication, e.g. wireless extensions ), 1), H04N19/177 (the unit being an image region, e.g. an object, 1)
With keywords such as: with, includes, that, disclosed, chamber, solder, paste, cartridge, body, connection in patent application abstracts.
Top Inventors:
- Thanh Tan NGUYEN of Ho-Chi-Minh City VN (1 patents)
- Samarth Manoj BRAHMBHATT of Mountain View CA US (1 patents)
- German ROS SANCHEZ of Mountain View CA US (1 patents)
- Shelby G. ROLLINS of Hillsboro OR US (1 patents)
- Sundar V. PATHY of Chandler AZ US (1 patents)
Patent Applications by Intel Corporation
20250178110. ENHANCED SOLDER PASTE DISPENSING TOOL METHOD (Intel)
Abstract: a solder paste cartridge is disclosed that includes a body with a connection arm and a chamber, which has a front wall with a first angled bottom panel and a back wall with a second angled bottom panel that form an unpartitioned space. in an aspect, a first lower edge of the first angled bottom panel and a second lower edge of the second angled bottom panel form an aperture for the chamber. in another aspect, a pushing member may be positioned between the front and back walls of the chamber and may have a first angled bottom surface and a second angled bottom surface. the pushing member may move from an upper position to a lower position in the chamber, which positions the first and second angled bottom surfaces of the pushing member approximal to the first and second angled bottom panels of the chamber.
20250178198. ROBOT SIMULATOR EFFICIENT CONTACT WRENCH ESTIMATION (Intel)
Abstract: disclosed herein are devices, methods, and systems for optimizing a robot simulator through calibration and/or training. the system collects real-world data points and simulation data points of a movement of a robot based on a heuristic policy that defines a threshold criterion for the movement of the robot. at least two data points of the simulation data points are time-aligned to corresponding data points of the real-world data points at times where the threshold criterion is satisfied. a transformation parameter is determined that is defined by a function that relates, for each simulation data point of the at least two data points and its corresponding real-world data point of the corresponding data points, a real-world magnitude of the real-world data point to a simulation magnitude of the simulation data point.
Abstract: a portion of test content to test a device under test (dut) in automatic test equipment (ate) is loaded by a controller in the ate in a memory partition in a channel card in the ate prior to start of the test of the dut. a next portion of the test content is dynamically loaded by the controller in another partition of the memory while the portion of test content is being used to test the dut. the size of the memory in the channel card is reduced because all test content for the test of the dut is not stored in the memory prior to start of the test of the dut.
Abstract: peripheral input devices including user presence detection sensors and related methods are disclosed herein. an example apparatus includes processor circuitry to execute instructions to cause a user device to transition from a first device state to a second device state in response to an indication of a first user presence state at a first time, the first user presence state relative to a peripheral input device communicatively coupled to the user device; cause the user device to transition from the second device state to a third device state in response to an indication of a second user presence state relative to the peripheral input device at a second time; and cause the user device to transition from the third device state to the first device state in response to an indication of the second user presence state relative to the peripheral input device at a third time.
20250181518. MANAGEMENT DEVICE UTILIZATION (Intel)
Abstract: examples described herein relate to a device that includes a host interface; circuitry coupled to the host interface; and second circuitry. the second circuitry is to limit usage of the circuitry, by a first process, by limiting performance of requests for translation of virtual memory addresses to physical memory addresses, from the first process. the circuitry includes one or more of: a network interface device, an accelerator, memory, or storage.
20250181667. HARDWARE ACCELERATION CLIFFORD ALGEBRAIC OPERATIONS (Intel)
Abstract: an apparatus may compute geometric products of blades. the apparatus may include a register, sign compute block(s), parity block(s), and an xor gate. the register may store a first bit operand representing which base(s) are included in a first blade and a second bit operand representing which base(s) are included in a second blade. the sign compute block(s) may determine one or more signs from the bit operands. a sign may indicate whether a product of multiplying base(s) in the first blade by base(s) in the second blade is positive or negative. each parity block is paired with a sign compute block. each parity block may determine whether to change a sign determined by the pairing sign compute block. the xor gate may determine a sign for the geometric product of the first blade and the second blade from outputs of the sign compute block(s) and the parity block(s).
20250181782. PHYSICAL COMPUTER INTRUSION DETECTION (Intel)
Abstract: an apparatus includes a circuit board configured for attachment to a cover by a first fastener. the circuit board includes a first via sized to receive a distal portion of a first shaft of the first fastener. a first upper portion of the first shaft is to be received in a through-hole in the cover. the apparatus further includes a first conductive trace extending from a first side wall defining the first via to first circuitry. the first conductive trace is configured to carry one or more input signals to the first circuitry indicating whether the distal portion of the first shaft is at least partially disposed in the first via and communicatively coupled to a first conductive element associated with the first via. the first conductive element may include a first conductive plating at least partially covering the first side wall defining the first via.
20250182709. GLARE OCCLUDED VIEW COMPENSATION AUTOMOTIVE OTHER APPLICATIONS (Intel)
Abstract: often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. however, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. embodiments are directed to eliminating such glare. other embodiments are related to mixed reality (mr) and filling in occluded areas.
20250183067. MODULAR EQUIPMENT MAINFRAME SEMICONDUCTOR PROCESS FLOWS (Intel)
Abstract: mainframes and systems for semiconductor device manufacturing are disclosed herein. in one embodiment, a mainframe includes one or more racks to removably couple process modules, where the process modules are to be arranged in rows, and one or more robots in a lane between the rows to transfer semiconductor workpieces to and from the process modules.
20250183179. PASSIVE STRUCTURES EMBEDDED BRIDGE ARCHITECTURES (Intel)
Abstract: embodiments disclosed herein comprise bridge dies with embedded passive components. in an embodiment, the bridge die is an apparatus that comprises a substrate with a via at least partially through a thickness of the substrate. in an embodiment, the via is electrically conductive. in an embodiment, a shell is provided around a perimeter of the via, and the shell is a different material than the via.
20250183180. DIRECT BONDING EMBEDDED BRIDGES VIAS (Intel)
Abstract: embodiments disclosed herein include package substrates with bridge dies. in an embodiment, an apparatus comprises a first layer that is a glass layer. a via is provided through the first layer, where the via is electrically conductive. in an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. in an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. in an embodiment, a die is in the cavity. in an embodiment, the die is electrically coupled to the via.
Abstract: a method and apparatus for protecting receiver circuitry from damage from interference signals. the apparatus includes a digital step attenuator (dsa) configured to attenuate a received signal, an over-voltage detector configured to detect a peak of the received signal at an input of receiver circuitry and activate an over-voltage detection signal if the peak of the received signal exceeds a detection threshold, and a digital control block configured to send a control code to the dsa to control an attenuation step of the dsa. the digital control block sends a control code to set the attenuation step of the dsa at a pre-configured attenuation step in response to the over-voltage detection signal asserted by the over-voltage detector. the pre-configured attenuation step is set to a level that can protect the receiver circuitry from the interference signals.
Abstract: method and apparatus for skew error measurement and correction in a digital-to-analog converter (dac) using a time-to-digital converter (tdc). a dac includes a main dac and a tdc. the main dac includes a plurality of dac cells. the main dac is configured to generate an analog output signal based on digital input data. the tdc is coupled to an output of the main dac and configured to measure a timing error of the main dac. the timing error may be measured on a dac cell basis or a subset of dac cells basis.
Abstract: a base station operates in a massive multiple-input multiple-output (mimo) and includes an antenna array comprising a plurality of antenna elements, radio frequency circuitry comprising a plurality of radio frequency (rf) chains coupled to a plurality of antennas from an antenna array and are configured to create radio frequency signals from baseband signals. the baseband circuitry includes at least one processor and coupled to the rf circuitry, the base band circuitry configured to cause the apparatus to implement a dynamic power efficiency operation based on current network traffic requirements.
20250184050. BANDWIDTH PART (BWP) OPERATION COLLISION HANDLING FULL DUPLEX COMMUNICATIONS (Intel)
Abstract: a user equipment (ue) configured for operation in a fifth-generation new radio (5g nr) network may decode resource configuration information received from a generation node b (gnb) for non-overlapping sub-band full duplex (nosb-fd) communication. the resource configuration information may indicate downlink symbols within a carrier bandwidth for downlink communication, uplink symbols within the carrier bandwidth for uplink communication, and nosb-fd symbols within the carrier bandwidth. each nosb-fd symbol may be configurable for both uplink and downlink communication. for any one of the nosb-fd symbols, one or more uplink subbands within the carrier bandwidth may be configurable to be allocated for uplink communication and one or more downlink subbands of the carrier bandwidth may be configurable to be allocated for downlink communication. the resource configuration information may be determined from a mapping of physical resource blocks (prbs) to a common resource block (crb) grid.
20250184058. MECHANISMS MULTI-CARRIER TRANSMIT SWITCHING NEW RADIO SYSTEMS 5G RAN1 (Intel)
Abstract: an apparatus of a new radio (nr) node b (gnb), a method, and a storage medium. the apparatus is to perform operations including: identifying three or more bands for transmit (tx) switching by a user equipment (ue); and encoding for transmission a message to the ue to indicate the three or more bands for tx switching; and storing the three or more bands for tx switching.
20250184084. TIMING ADVANCE CHANNEL STATE INFORMATION ENHANCEMENTS (Intel)
Abstract: the present disclosure is generally related to wireless communications technologies, network topologies, and communication device implementations, and in particular, to multipletransmission reception point (multi-trp) uplink (ul) transmission schemes. the multi-trp ul transmission schemes include timing advance (ta) associations for multi-trp operation, channel state information (csi) enhancements, and codebook structural enhancements. to enhance the performance of rel-16 codebook, a new codebook structure is constructed by preserving the rel-16 codebook structure in the spatial dimension (sd) and frequency dimension (fd) while extending the rel-16 codebook in the time dimension (td) using a mutually orthogonal discrete fourier transform (dft) basis.
Abstract: methods and apparatus for a latent supplementary protocol (lsp) for enhancing performance and functionality of communication systems. the lsp implements a pam (pulse amplitude modulation) 6 (pam6) modulation scheme utilizing 36 constellation points comprising a multiplex of 32-qam and shifted 32-qam constellations, each comprising 32 pam6 symbols. supplementary data are added to constellation points comprising conveyors and shifted constellation points without affecting the bandwidth of transfer of payload data between link partners implementing the lsp. the supplementary data may be employed for various purposes, including but not limited to payload data protection, an auxiliary communication channel between link partners, and transfer of additional payload data.
20250184280. APPLICATION-LEVEL NETWORK QUEUEING (Intel)
Abstract: there is disclosed in one example a network interface card (nic), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.
Abstract: for example, a computing system may be configured to provide a first computing device and a second computing device, which is paired with the first computing device, with access to a subscription-restricted service of an application, for example, based on a subscription confirmation to confirm a subscription to the subscription-restricted service. for example, the computing system may be configured to identify a pairing between the first computing device and a third computing device, which is unsubscribed to the subscription-restricted service, and to assign the third computing device to the subscription and provide the third computing device with access to the subscription-restricted service, for example, based on the identification of the pairing between the first computing device and the third computing device.
20250184501. METHOD SYSTEM VIDEO PROCESSING LOW LATENCY BITSTREAM DISTRIBUTION (Intel)
Abstract: methods, systems, mediums, and devices use video processing with low latency bitstream distribution.
20250184685. SECURE MONOSTATIC WIRELESS PROXIMITY DETECTION SENSING (Intel)
Abstract: disclosed herein are devices, methods, and systems for wireless proximity detection of an object (e.g., a human user) with respect to a computing system. a proximity detection system may transmit a series of wireless signal frames, each including a signature that differs between consecutive frames of the series of transmitted wireless signal frames. the system may also determine a validated frame subset from among a series of received wireless signal frames based on whether the series of received wireless signal frames includes the signature corresponding to the series of transmitted wireless signal frames. the system may also determine a proximity of an object to a wireless antenna based on the validated frame subset. this signature may be randomized so as to provide improved security against spurious/fraudulently transmitted signal frames.
20250184973. ENHANCED FRAME TIME DOMAIN PREEMPTION (Intel)
Abstract: this disclosure describes systems, methods, and devices related to time domain preemption. a device may generate a frame comprising a preamble and a data payload. the device may divide the data payload into a plurality of data portions. the device may insert a time domain gap between each of the plurality of data portions to allow for preemption during transmission of the frame. the device may cause to send the frame to a first station device.
20250184976. IDENTIFYING INTERFERERS 60 GIGAHERTZ (Intel)
Abstract: this disclosure describes systems, methods, and devices related to 60 ghz interference detection. a device may establish a 60 ghz communication on a first frequency channel. the device may identify a frame received from an access point (ap) or a first station device, wherein the frame is a communication between the ap and the first station device on the first frequency channel. the device may extract information from the frame, wherein the information identifies whether the frame is from the ap or the first station device. the device may utilize a 60 ghz lower frequency channel to communicate with the ap or the first station device to indicate to the ap or the first station device to communicate using a different channel in a future communication.
Abstract: for example, a wireless communication device may be configured to generate a millimeter wave (mmwave) physical layer (phy) protocol data unit (ppdu) configured for transmission over an mmwave wireless communication channel according to an mmwave channelization scheme, the mm wave channelization scheme defining a plurality of mmwave channels in an mmwave wireless communication frequency band, wherein the plurality of mmwave channels are based on a minimal mm wave channel bandwidth (bw), wherein the minimal mm wave channel bw is equal to or greater than 80 megahertz (mhz) and not more than 640 mhz; and to transmit the mmwave ppdu over the mm wave wireless communication channel.
20250185080. PRACH DETECTION WIRELESS NETWORK (Intel)
Abstract: the present disclosure relates to a device including: a processor and a memory to: carry out a prach detection in a plurality of detection windows, each including a plurality of samples, wherein the prach detection includes, for each detection window: comparing a power value of each sample with a predefined threshold power; and after having carried out the comparison for all the samples: if the power value of at least one sample is greater than the predefined threshold power, identifying the sample having the greatest power value, and generating a result signal indicative of a successful prach detection and of a position of the identified sample; if all the samples have a power value less than the predefined threshold power, refraining from searching the sample having the greatest power value. the predefined threshold power may include a plurality of threshold powers, to enable communication via a plurality of communication paths.
Abstract: embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. in an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. the first semiconductor layers may have a first spacing. in an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. the semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. in an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.
20250185363. FORKSHEET TRANSISTORS DIELECTRIC OR CONDUCTIVE SPINE (Intel)
Abstract: embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. for example, an integrated circuit structure includes a dielectric spine. a first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. a second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. an n-type gate structure is on the first vertical stack of semiconductor channels, a portion of the n-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. a p-type gate structure is on the second vertical stack of semiconductor channels, a portion of the p-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.
