Intel Corporation patent applications on 2025-05-29
Patent Applications by Intel Corporation on May 29th, 2025
Intel Corporation: 34 patent applications
Intel Corporation has applied for patents in the areas of G01R31/3187 (MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits ), 1), H02J7/0029 (Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries, 1), H10D30/798 (No explanation available, 1), H10B10/125 (ELECTRONIC MEMORY DEVICES, 1), H04W76/15 (Setup of multiple wireless link connections, 1), H04W74/0808 (using carrier sensing, e.g. carrier sense multiple access [CSMA], 1), H04W72/25 (WIRELESS COMMUNICATION NETWORKS (broadcast communication ; communication systems using wireless links for non-selective communication, e.g. wireless extensions ), 1), H04W52/0235 (WIRELESS COMMUNICATION NETWORKS (broadcast communication ; communication systems using wireless links for non-selective communication, e.g. wireless extensions ), 1), H04N19/70 (characterised by syntax aspects related to video coding, e.g. related to compression standards, 1), H04L67/1001 (for accessing one among a plurality of replicated servers, 1)
With keywords such as: circuit, apparatus, includes, circuitry, embodiment, test, operations, execute, functional, infield in patent application abstracts.
Top Inventors:
- Rakesh Kandula of Bangalore IN (1 patents)
- Fei Su of Ann Arbor MI US (1 patents)
- Ophir Shabtay of Tsofit IL (1 patents)
- Kobi Ben Atar of Mazkeret Batya IL (1 patents)
- Sharon Heruti of Tel-Aviv IL (1 patents)
Patent Applications by Intel Corporation
20250172611. PREDICTIVE ADAPTIVE INFIELD TESTING BASED SILICON HEALTH INFORMATION (Intel)
Abstract: in one embodiment, an apparatus includes: a functional circuit to execute operations; test circuitry to execute infield testing of at least a portion of the functional circuit; a plurality of sensors to sense sensor information; and a test controller coupled to the test circuitry, the test controller to prevent at least a portion of the test circuitry from execution of the infield testing based at least in part on the sensor information. other embodiments are described and claimed.
20250172682. RADAR APPARATUS, SYSTEM, METHOD (Intel)
Abstract: for example, an apparatus may include a communication interface configured to communicate with a plurality of radio heads (rhs); and a processor configured to coordinate radar communications by the plurality of rhs and to generate radar information based on the radar communications by the plurality of rhs. the processor may be configured to transmit synchronization information to the plurality of rhs via the communication interface, the synchronization information configured to synchronize the radar communications by the plurality of rhs; and to communicate at least one of radar transmit (tx) information or radar receive (rx) information with the plurality of rhs via the communication interface.
20250172967. HINGED COMPUTING DEVICES HAVING INTRA-DEVICE WIRELESS COMMUNICATIONS (Intel)
Abstract: hinged computing devices having intra-device wireless communications are disclosed. a disclosed example apparatus for use with a foldable computing device includes a hinge by which first and second folding portions of the computing device are rotatably coupled, a first antenna of the first folding portion, a second antenna of the second folding portion, the first and second antennas to be wirelessly communicatively coupled to one another, the first and second antennas separate from the hinge, and equalizer circuitry to enable equalization between the first and second antennas to maintain signals therebetween to meet a bit error rate (ber) threshold over a range of motion of the first folding portion relative to the second folding portion.
20250173089. CROSS-DOMAIN SOLUTION FABRIC (Intel)
Abstract: a network processing device implements a cross-domain solution (cds) and includes a shared memory, an i/o interface, a network interface, and a cds manager to create a buffer in the shared memory to allow writes by a first software module in a first domain and reads by a second software module in a second domain, where the reads are received from the second software module over a network connection facilitated by the network interface. the buffer is used to implement a memory-based communication channel between the first software module and the second software module, where the first domain is independent of the second domain.
Abstract: apparatus and methods for true random number generation (rng) with a target probability distribution with autonomously learning probabilistic circuits. the apparatus utilizes, for individual probabilistic bits (p-bits), a magnetic tunnel junction (mtj) resistor. the apparatus also uses circuitry to harness the fluctuating resistance of the mtj resistor to generate high-quality random numbers. the hardware footprint depends on the precision required and is smaller than an equally precise or high-quality rng implemented using cmos hardware. post-processing is not required on the generated random numbers.
20250173149. APPARATUS METHOD RECONCILING CONFLICTING CACHELINE MODIFICATIONS (Intel)
Abstract: apparatus and method for reconciling cache line modifications. for example, one embodiment of a processor comprises: a plurality of instruction processing pipelines, each instruction processing pipeline to process sequences of instructions; an interconnect coupled to the plurality of instruction processing pipelines; and a memory subsystem coupled to plurality of instruction processing pipelines over the interconnect, the memory subsystem comprising a plurality of atomic operation circuits corresponding to a plurality of memory interfaces to be coupled to a corresponding plurality of memories, each atomic operation circuit configured to perform a corresponding reduction operation with first data stored in the memory and second data indicated in a command packet, the atomic operation circuit to generate result data based on the reduction operation which is to be stored in the memory.
20250173157. Apparatus, Device, Method, Computer Program Computer System (Intel)
Abstract: examples relate to a computer system and to an apparatus device method, and computer program for a computer system. the apparatus comprises processing circuitry is configured to detect the presence of a peripheral device connected to the computer system. the processing circuitry is configured to add the peripheral device to a device tree managed by a firmware of the computer system, by adding a first and a second device node to the device tree, the first device node representing the peripheral device and the second device node representing a reset capability or firmware flash capability of the peripheral device.
Abstract: techniques for debugging a confidential virtual machine for a processor in production mode are described. in certain examples, a hardware processor core is to implement: a trust domain manager to manage one or more hardware isolated virtual machines as a respective trust domain with a region of memory protected by a respective encryption key, and a virtual machine monitor that is not allowed access to the protected region of memory of the one or more hardware isolated virtual machines; and a memory management circuit coupled between the hardware processor core and the memory, wherein, in response to a hardware isolated virtual machine generating a memory dump file, the trust domain manager is to encrypt the memory dump file with a debug key that is different from any of the respective encryption key to generate an encrypted memory dump file, and store the encrypted memory dump file in a portion of the memory that is accessible by the virtual machine monitor.
20250173231. APPARATUS METHOD CONTROLLING DEBUGGING HARDWARE LOCKSTEP MIS-COMPARES (Intel)
Abstract: an apparatus and method for controlling and debugging hardware lockstep mis-compares. for example, one embodiment of a processor comprises: a plurality of processing elements operable in a redundancy mode, the plurality of processing elements to each execute a same plurality of instructions and produce a corresponding plurality of result signals; comparator circuitry to compare corresponding result signals of the plurality of result signals, the comparator circuitry to generate one or more failure indications when a first one or more result signals produced by a first processing element are different from a corresponding second one or more result signals produced by a second processing element; and masking circuitry to mask a first failure indication of the one or more failure indications when a corresponding mask bit of a mask matrix is set to a first value.
20250173258. Concept Providing Access Persistent Memory (Intel)
Abstract: examples relate to an apparatus, a device, a method, and a computer program for a computer system, and to a corresponding computer system. the apparatus comprises circuitry config-ured to provide an interface for accessing persistent memory provided by persistent memory circuitry of the computer system from one or more software applications. the circuitry is configured to translate instructions for performing operations on the persistent memory into corresponding instructions for offloading circuitry of the computer system, the corresponding instructions being suitable for instructing the offloading circuitry to perform the operations on the persistent memory. the circuitry is configured to provide the access to the persistent memory via the offloading circuitry.
20250173288. DIRECT-MEMORY TRANSACTIONS CROSS-DOMAIN SOLUTION (Intel)
Abstract: a cross-domain device includes a memory with a shared memory region, a first interface to couple to a first device over a first interconnect, and a second interface to couple to a second device over a second interconnect. a cross-domain solutions (cds) manager is provided, which is executable to implement a queue in the shared memory region, and use a direct memory access (dma) to write data from the queue to a memory of the second device associated with an application executed in the second domain.
20250173308. GRAPHICS PROCESSOR DATA ACCESS SHARING (Intel)
Abstract: embodiments are generally directed to graphics processor data access and sharing. an embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.
20250173567. INCREMENTAL PRECISION NETWORKS USING RESIDUAL INFERENCE FINE-GRAIN QUANTIZATION (Intel)
Abstract: one embodiment provides for a computer-readable medium storing instructions that cause one or more processors to perform operations comprising determining a per-layer scale factor to apply to tensor data associated with layers of a neural network model and converting the tensor data to converted tensor data. the tensor data may be converted from a floating point datatype to a second datatype that is an 8-bit datatype. the instructions further cause the one or more processors to generate an output tensor based on the converted tensor data and the per-layer scale factor.
20250173956. INFERRED SHADING MECHANISM (Intel)
Abstract: an apparatus to facilitate inferred object shading is disclosed. the apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3d) geometry, latent space and representation of the one or more objects.
Abstract: described herein are ic devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (dsa)-enabled process with dsa assisting features. a patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. the dsa assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.
20250174523. NESTED ARCHITECTURES ENHANCED HETEROGENEOUS INTEGRATION (Intel)
Abstract: embodiments disclosed herein include electronic packages and methods of forming such electronic packages. in an embodiment, the electronic package comprises a base substrate. the base substrate may have a plurality of through substrate vias. in an embodiment, a first die is over the base substrate. in an embodiment a first cavity is disposed into the base substrate. in an embodiment, the first cavity is at least partially within a footprint of the first die. in an embodiment, a first component is in the first cavity.
20250174922. DAMPING ELEMENTS PIN VIBRATION FRETTING RISK MITIGATION (Intel)
Abstract: embodiments disclosed herein include an apparatus for socket interconnects. in an embodiment, the apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. in an embodiment, a first pin extends from the first surface, and a second pin extends from the second surface. in an embodiment, a first pad is on the first surface, where the first pad is electrically insulating. in an embodiment, a second pad is on the second surface, where the second pad is electrically insulating.
20250174963. INTEGRATED DENSE WAVELENGTH DIVISION MULTIPLEXED LASER ARRAY (Intel)
Abstract: integrated laser arrays, photonic devices, packages, and systems are disclosed. an example integrated laser array includes first and second lasers, each laser including a light-emitter structure and a waveguide with a grating. in one aspect, effective pitches of the gratings of the first and second lasers are different by less than about 5 angstroms, while the gratings of the first and second lasers are fabricated with a resolution of at least 1 nanometer. in another aspect, each laser includes a waveguide with left and right sidewall gratings, effective widths of the waveguides of the first and second lasers are different, and an offset between the left and right sidewall gratings of the second laser is different from an offset between the left and right sidewall gratings of the first laser. integrated laser arrays described herein may be particularly suitable for being implemented in dense wavelength division multiplexed systems.
20250175019. INRUSH CURRENT REGULATION BATTERY CHARGER TOPOLOGY (Intel)
Abstract: the disclosed techniques include reducing inrush current due to the bulk capacitance by pre-charging the bulk capacitance using a charge from a battery provided by a battery charging circuit. an example apparatus includes a switching circuit with an input terminal and an output terminal. the input terminal of the switching circuit is coupled to a power adapter. the apparatus includes a battery charging circuit with a first terminal and a second terminal. the first terminal of the battery charging circuit is coupled to the output terminal of the switching circuit. the second terminal of the battery charging circuit is coupled to a battery. the apparatus includes a bypass circuit with an input terminal and an output terminal, with its input terminal coupled to the output terminal of the switching circuit and the first terminal of the battery charging circuit. the apparatus includes a bulk capacitor coupled to the bypass circuit.
20250175202. SWITCH CIRCUITS, ATTENUATION CIRCUITS, RECEIVERS, BASE STATION MOBILE DEVICE (Intel)
Abstract: a switch circuit is provided. the switch circuit includes a first node for coupling to a first conductive path and a second node for coupling to a second conductive path. additionally, the switch circuit includes first and second stacks of transistors arranged between the first and second nodes. a first transistor of the first stack and a first transistor of the second stack are respectively cross-coupled with a second transistor of the second stack and a second transistor of the first stack. the first transistors of the first and the second stack are coupled to the first node. a third transistor of the first stack and a third transistor of the second stack are respectively cross-coupled with a fourth transistor of the second stack and a fourth transistor of the first stack. the fourth transistors of the first and the second stack are coupled to the second node.
Abstract: for example, an ap device may be configured to transmit a beamforming training trigger frame from a sub-10 ghz ap of the ap device over a sub-10 ghz wireless communication channel, the beamforming training trigger frame including configuration information to configure beamforming training over a mmwave wireless communication channel; to transmit a sequence of training frames from a mmwave ap of the ap device over the mm wave wireless communication channel after the beamforming training trigger frame, the sequence of training frames includes one or more sector-based training sequences according to the configuration information, wherein a sector-based training sequence includes transmission of one or more training frames according to the configuration information; and to process a feedback frame from a non-ap device to identify feedback information based on the sequence of training frames.
20250175282. ASYNCHRONOUS INPUT DEPENDENCY RESOLUTION MECHANISM (Intel)
Abstract: described herein is a graphics processor configured to perform asynchronous input dependency resolution among a group of interdependent workloads. the graphics processor can dynamically resolve input dependencies among the workloads according to a dependency relationship defined for the workloads. dependency resolution be performed via a deferred submission mode which resolves input dependencies prior to thread dispatch to the processing resources or via immediate submission mode which resolves input dependencies at the processing resources.
20250175317. SELF-CLOCKED DUTY-CYCLE CORRECTED CURRENT-INTEGRATING PHASE INTERPOLATOR (Intel)
Abstract: embodiments herein relate to a phase interpolator for interpolating phases of input clock signals. in a series of interpolating cells, each cell receives clock signals having a phase offset between them and outputs an interpolated clock signal having a phase between the phases of the input clock signals. the received clock signals control the on and off time for first and second current sources of the interpolator cell. additionally, a pulldown transistor is controlled by an internally-generated clock signal from a previous cell in the series, and each cell outputs an internally-generated clock signal that is fed to the next cell in the series to control its pulldown transistor. as a result, the duty cycle of the interpolated clock signal is made constant. a programmable common mode voltage removes any systematic direct current (dc) error in transferring the pulldown signal from one interpolator cell to another.
20250175431. METHODS ARRANGEMENTS SERVICE FUNCTION CHAINING PACKET STEERING (Intel)
Abstract: logic may identify, based on a service request received via the network interface, a service function chain comprising one or more instances of communication service functions, computing service functions, and data service functions in a network, wherein the one or more instances of communication service functions are associated with one or more instances of computing service functions and the one or more instances of data service functions. logic may determine service-aware transport information associated with the service function chain. logic may configure, via the one or more interfaces, the one or more instances of communication service functions, computing service functions, and data service functions for packet steering based on the service-aware transport information. and logic may parse a service label of a packet associated with a service identified in the service request to determine the service label and forward the packet to a service function based on the service label.
20250175436. TECHNOLOGIES PROTOCOL-AGNOSTIC NETWORK PACKET SEGMENTATION (Intel)
Abstract: technologies for protocol-agnostic network packet segmentation includes determining whether a size of a payload of a network packet to be transmitted by the compute device exceeds a maximum size threshold and segmenting the payload into a plurality of segmented payloads if the size of the payload exceeds the maximum size of threshold. the payload may be segmented based on segmentation metadata associated with the network packet.
20250175518. MULTI-TENANT ISOLATED DATA REGIONS COLLABORATIVE PLATFORM ARCHITECTURES (Intel)
Abstract: a multi-tenant dynamic secure data region in which encryption keys can be shared by services running in nodes reduces the need for decrypting data as encrypted data is transferred between nodes in the data center. instead of using a key per process/service, that is created by a memory controller when the service is instantiated (for example, mktme), a software stack can specify that a set of processes or compute entities (for example, bit-streams) share a private key that is created and provided by the data center.
Abstract: this disclosure describes systems, methods, and devices related to enhanced low complexity enhancement video coding (lcevc) presentation of tiles. a device may encode video data into one or more bits while applying an lcevc organizational syntax. the device may generate a bitstream of the one or more bits based on the lcevc organizational syntax. the device may assign a payload type value to the bitstream, wherein the payload type value indicates the lcevc organizational syntax has been applied to the one or more bits. the device may transmit the bitstream to a device comprising a decoder.
20250175899. RESOURCE DETERMINATION LOW POWER WAKE-UP SIGNAL (Intel)
Abstract: various embodiments herein provide techniques related to transmission of a wake-up signal (wus) from a base station to a user equipment (ue). in embodiments, the wus may be received by a wake-up receiver (wur) of the ue. based on reception of the wus, a main receiver of the ue may exit from a deep-sleep state or an off state. other embodiments may be described and/or claimed.
20250175999. MULTIPLEXING MECHANISMS SL PRS PSCCH TRANSMISSION (Intel)
Abstract: an apparatus and system of providing a sidelink position reference signal (sl prs) and physical sidelink control channel (pscch) transmission are described. the pscch, which carries sidelink control information (sci), and sl prs are time division multiplexed (tdmed) in a particular slot. the pscch is transmitted in a dedicated resource pool for sl prs that includes a dedicated resource region allocated for the pscch transmission. the sl prs is transmitted in a shared resource pool for sl communication and the sl prs. a sl prs resource index is indicated in a second stage sci carried by a physical sidelink shared channel (pssch), which is tdmed with the pscch and the sl prs. a starting symbol and/or length of the sl prs is predefined in the 3 gpp specification or (pre-)configured by higher layer signaling.
Abstract: various embodiments herein relate to identifying an indication of a channel access priority class (capc); identifying, based on the capc and a table related to the capc, a length of a channel occupancy time (cot); and participating in a sidelink (sl) communication in the unlicensed spectrum based on the cot. other embodiments may be described and/or claimed.
20250176048. MULTI-LINK RE-SETUP LINK CHANGE (Intel)
Abstract: this disclosure describes systems, methods, and devices related to an extreme high throughput (eht) signaling structure. a device may establish a communication channel with one or more station devices (stas). the device may generate an extreme high throughput signal field (eht-sig) of a header, wherein the eht-sig field comprises information associated with resource allocations (rus). the device may generate a frame comprising the header. the device may assign a first ru to a first station device. the device may assign a second ru to the first station device, wherein the first ru or the second ru is an aggregation of a 26-tome ru and a neighboring ru. the device may cause to send the frame to the first station device.
Abstract: integrated circuit structures having uniform grid metal gate and trench contact cut with channel depopulation, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut with channel depopulation, are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires. a gate electrode is over the vertical stack of horizontal nanowires. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. a first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. a second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.
Abstract: fin trim plug structures for imparting channel stress are described. in an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. the fin has a trench separating a first fin portion and a second fin portion. a first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. a second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. an isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. the isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.
20250176255. BACK-SIDE NANORIBBON REMOVAL (Intel)
Abstract: fabrication methods for integrated circuit (ic) structures and devices involving back-side nanoribbon removal are described herein. in one example, back-side nanoribbon removal involves providing stacks of nanoribbons from a first side of an ic structure, followed by removing one or more of the nanoribbons from a second side that is opposite the first side. in one example, an ic structure fabricated with back-side nanoribbon removal techniques may include a first stack of nanoribbons over a support and a second stack of nanoribbons over the support, where the number of nanoribbons in the first stack is less than in the second stack. a first transistor includes first channel regions in the nanoribbons of the first stack and a second transistor includes second channel regions in the nanoribbons of the second stack. therefore, in one such example, the first transistor has channel regions in fewer nanoribbons than the second transistor.