Intel Corporation patent applications on 2025-05-22

Patent Applications by Intel Corporation on May 22nd, 2025

Intel Corporation: 15 patent applications

Intel Corporation has applied for patents in the areas of G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining, 2), G03F1/84 (PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices ; photosensitive materials or processes for photographic purposes ; electrophotography, sensitive layers or processes therefor ), 1), G06F13/4022 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models ), 1), G06F16/532 (Query formulation, e.g. graphical querying, 1), G06N3/065 (Analogue means, 1), H01L23/3192 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application), 1), H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application), 1), H01L25/105 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (use of semiconductor devices for measuring ; resistors in general ; magnets, inductors or transformers ; capacitors in general ; electrolytic devices ; batteries or accumulators ; waveguides, resonators or lines of the waveguide type ; line connectors or current collectors ; stimulated-emission devices ; electromechanical resonators ; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers ; electric light sources in general ; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components ; use of semiconductor devices in circuits having a particular application, see the subclass for the application), 1), H04B1/04 (Circuits, 1), H04L9/3268 ({using certificate validation, registration, distribution or revocation, e.g. certificate revocation list [CRL]}, 1)

With keywords such as: apparatus, methods, photomask, systems, articles, manufacture, improve, detection, defects, blanks in patent application abstracts.

Top Inventors:

• Yoshihiro Tezuka of Tsukuba JP (1 patents)
• Annelise Rachel Beck of Sunnyvale CA US (1 patents)
• Chang Ju Choi of Fremont CA US (1 patents)
• Eric Alan Frendberg of Dublin CA US (1 patents)
• Richard Seiji Oka of San Jose CA US (1 patents)

Patent Applications by Intel Corporation

20250164871. METHODS APPARATUS IMPROVE DETECTION DEFECTS PHOTOMASK BLANKS (Intel)

Abstract: systems, apparatus, articles of manufacture, and methods to improve detection of defects in photomask blanks are disclosed. an example apparatus includes: interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: identify a first potential defect in a photomask blank based on an intensity value not satisfying a first threshold but satisfying a second threshold, the intensity value based on pixel data associated with a first type of inspection of the photomask blank; and designate the first potential defect as a detected defect based on first coordinates for the first potential defect being within a threshold distance of second coordinates for a second potential defect, the second potential defect identified based on a second type of inspection of the photomask blank.

20250165424. HIGH BANDWIDTH CORE NETWORK-ON-CHIP INTERFACE (Intel)

Abstract: an apparatus includes a first port set that includes an input port and an output port. the apparatus further includes a plurality of second port sets. each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. the plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

20250165522. Perform Image Simularity Search one or More Generated Images (Intel)

Abstract: image similarity search results can be improved by augmenting a query image with images that are generated based on the query image. the generated images can have different camera poses, different lighting conditions, etc. the generated images can be generated using machine learning models. using an ensemble of images having the query image and the generated images when searching a library of candidate images can improve performance of image similarity search. producing effective generated images is not trivial. also, an image similarity search algorithm may be modified to identify and rank top matching images that are most similar to the ensemble of images.

20250165765. COMBINATORIAL OPTIMIZATION ACCELERATED PARALLEL, SPARSELY COMMUNICATING, COMPUTE-MEMORY INTEGRATED HARDWARE (Intel)

Abstract: a neuromorphic network may solve combinatorial optimization problems. the neuromorphic network may include variable neurons, a solution monitoring neuron, and one or more readout neurons. the variable neurons may each represent one binary variable in a combinatorial optimization problem. an internal state of a variable neuron may change as the variable flips. the internal state may be stored in a memory of the variable neuron. the variable neuron may spike when its internal state changes. one or more other variable neurons receiving the spike may determine whether to change their internal states based on the spike. the variable neurons may send their internal states to the solution monitoring neuron to compute a cost of the qubo problem and determine whether a solution is found. a readout neuron may receive variable assignments resulting in the solution from at least some variable neurons and integrate the variable assignments into one message.

20250166114. ARCHITECTURE BLOCK SPARSE OPERATIONS SYSTOLIC ARRAY (Intel)

Abstract: embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. one embodiment provides for data aware sparsity via compressed bitstreams. one embodiment provides for block sparse dot product instructions. one embodiment provides for a depth-wise adapter for a systolic array.

20250166115. COMPUTE OPTIMIZATION MECHANISM DEEP NEURAL NETWORKS (Intel)

Abstract: embodiments provide mechanisms to facilitate compute operations for deep neural networks. one embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. the plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. the first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

20250167062. MICROELECTRONIC STRUCTURES INCLUDING BRIDGES (Intel)

Abstract: disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. in some embodiments, a microelectronic structure may include a substrate and a bridge.

20250167180. INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK (Intel)

Abstract: embodiments of the present disclosure are directed towards an integrated circuit (ic) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. the first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. the ic package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. the second side may be disposed opposite to the first side. the second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

20250167183. FAN OUT PACKAGING POP MECHANICAL ATTACH METHOD (Intel)

Abstract: embodiments include semiconductor packages and a method of forming the semiconductor packages. a semiconductor package includes a mold over and around a first die and a first via. the semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. the semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. the first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

20250167818. Time encoded data communication protocol, apparatus method generating receiving data signal (Intel)

Abstract: an apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. an output interface circuit is configured to output the data signal.

20250168018. TECHNIQUES IMPLEMENT CONFIDENTIAL COMPUTING REMOTE DEVICE VIA USE TRUST DOMAINS (Intel)

Abstract: examples include techniques to implement confidential computing with a remote device via use of trust domains. examples are described of establishing secure communication sessions between a trust domain supported by a hardware processor core on a first host platform and an input/output (i/o) device resident on a second host platform.

20250168627. REDUCTION TIME-DOMAIN CORRELATION SECURE SOUNDING SIGNAL (Intel)

Abstract: this disclosure describes systems, methods, and devices related to correlation reduction. a device may generate a sequence of pseudo-random symbols associated with a sounding signal to be transmitted to a first station device. the device may apply a modifier to the sequence of pseudo-random symbols. the device may generate a secure sounding signal from the modified sequence of pseudo-random symbols. the device may send the secure sounding signal to a first station device.

20250168635. AUTHENTICATION AUTHORIZATION LOCALIZED SERVICES (Intel)

Abstract: the present disclosure provides technologies and techniques related to enabling access to localized services. the present disclosure provides mechanisms for authentication and authorization for enabling a non-public network (npn) to act as a hosting network for providing access to localized services. additionally, the present disclosure provides mechanisms for enabling user equipment (ue) to discover, select and access an npn acting as a hosting network to receive localized services. furthermore, the present disclosure provides mechanisms for enabling access to localized services via a specific hosting network.

20250169027. METHODS APPARATUS ENHANCE COOLING COMPUTING DEVICES (Intel)

Abstract: systems, apparatus, articles of manufacture, and methods to enhance cooling of computing devices are disclosed. an example apparatus includes a blower housing, and an impeller carried by the blower housing. the impeller is to rotate to force air out through an outlet of the blower housing. the example apparatus further includes an ionic cooling system carried by the blower housing. the ionic cooling system is to force air out through the outlet of the blower housing.

20250169130. INTEGRATED CIRCUIT STRUCTURES DIFFERENT NANORIBBON THICKNESSES (Intel)

Abstract: fabrication methods for integrated circuit (ic) structures and devices with different nanoribbon thicknesses are disclosed. in one example, an ic structure includes a stack of nanoribbons stacked above one another over the support, including a first nanoribbon with a first channel region and a second nanoribbon with a second channel region, where the first channel region has a first thickness and the second channel region has a second thickness, and where the first thickness of the first channel region is different (e.g., greater) than the second thickness of the second channel region.