Patent Applications by Intel Corporation on 14th August 2025

Intel Corporation: 17 patent applications

Intel Corporation has applied for patents in the areas of H10D30/6757 (Technology classification, 3), G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining, 2), G06T15/005 ({General purpose rendering architectures}, 2), H10D88/00 (Technology classification, 2), H10D30/6735 (Technology classification, 2), H10D30/43 (Technology classification, 2), H10D62/121 (Technology classification, 2), H10D84/83 (Technology classification, 2), G06F21/64 (Protecting data integrity, e.g. using checksums, certificates or signatures, 1), G06F21/107 ({License processing; Key processing}, 1)

Top Inventors:

Jiewen Yao of Shanghai CN (1 patents)
Subrata Banik of Bangalore IN (1 patents)
Rajesh Poornachandran of Portland OR US (1 patents)
Vincent Zimmer of Issaquah WA US (1 patents)
Anbang Yao of Beijing CN (1 patents)
Chao Li of Beijing CN (1 patents)
Yangyuxuan Kang of Beijing CN (1 patents)
Dongqi Cai of Beijing CN (1 patents)
Xiaolong Liu of Beijing CN (1 patents)
Yi Yang of Gilbert AZ US (1 patents)

Patent Applications by Intel Corporation

20250258963. CONFIDENTIAL COMPUTE ARCHITECTURE FOR SILICON INITIALIZATION FOR IP PROTECTION AND ASSURANCE

Abstract: Embodiments are directed to utilizing a confidential compute architecture for silicon initialization for IP protection and assurance. An embodiment of a processing system includes a memory device communicably coupled to hardware components and to memory modules, the memory device to store platform i...

20250259055. NEURAL NETWORK WITH POINT GRID CONVOLUTIONAL LAYER

Abstract: A PGConv layer extract features from grid-structured data samples. The PGConv layer may receive an input feature map including a grid representation of an object, which is generated from a graph representation of the object. The grid representation includes node elements that are arranged in a grid ...

20250259336. INTERLEAVING OF VARIABLE BITRATE STREAMS FOR GPU IMPLEMENTATIONS

Abstract: Interleaving of variable bitrate streams for GPU implementations is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a super-compression encoder pipeline to provide variable width interleaved coding; and memory for ...

20250259370. LEARNING NEURAL REFLECTANCE SHADERS FROM IMAGES

Abstract: Described herein are techniques for learning neural reflectance shaders from images. A set of one or more machine learning models can be trained to optimize an illumination latent code and a set of reflectance latent codes for an object within a set of input images, such as lighting-based material e...

20250259371. DYNAMIC ROUTING OF TEXTURE LOADS IN GRAPHICS PROCESSING

Abstract: Dynamic routing of texture-load in graphics processing is described. An example of a processor includes one or more processing resources, the one or more processing resources to load a message including a texture load; a texture sampler and a data port; and a message router to route the texture load...

20250259542. ROAD HAZARD COMMUNICATION

Abstract: Apparatus, systems, and/or methods may involve reporting a road hazard. Road hazard data may be collected for an object on a road, which may include automatically generated data from a device associated with the object causing a hazard. The road hazard data may be provided to a service, an applicati...

20250259906. THERMAL PERFORMANCE IN HYBRID BONDED 3D DIE STACKS

Abstract: Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more therm...

20250259931. GRADUATED ETCH STOP FOR METALLIZATION LAYERS OF INTEGRATED CIRCUITS

Abstract: A graduated etch stop layer is included within a metallization stack of an integrated circuit device. The graduated etch stop layer has a higher concentration of a dopant at an upper portion of the layer than at a lower portion of the layer. The dopant may be oxygen, which reduces capacitance betwee...

20250260167. COIL FOR MOBILE DEVICE CONTEXT-DRIVEN SWITCHING AND WIRELESS CHARGING

Abstract: Apparatus, system and method to provide switchable coils in a computing device, comprising: a plurality of electrically conductive coils to transfer electromagnetic energy; a sensor coupled to a processor, to select a coil from among the plurality of electrically conductive coils; a switch to energi...

20250260498. CONFIGURING MARGINS FOR SINGLE ANTENNA REDUCED CAPABILITY USER EQUIPMENT

Abstract: Embodiments attempt to solve challenges in a wireless communications system. Embodiments describe various techniques, systems, and devices to support relaxed measurement criteria for reduced capability devices in a 3GPP 5G NR system, among other wireless communications systems. Other embodiments are...

20250260990. MITIGATION OF TOKEN REUSE ATTACKS

Abstract: Systems and methods are disclosed for secure token verification. A Network Repository Function (NRF) receives an access token request from a Network Function (NF) Service Consumer and generates an access token with enhanced security claims of authorized producer NF instances and a token issuance tim...

20250261240. SYSTEMS AND METHODS FOR RELAXED PROCESSING TIME FOR REDCAP DEVICES

Abstract: Various embodiments herein provide techniques for reduced capability (RedCap) user equipments (UEs). For example, embodiments relate to a relaxed (longer) timeline requirement associated with a random access procedure and/or other communications of RedCap UEs. The techniques may support existing Red...

20250261300. METHODS AND APPARATUS TO COOL HOTSPOTS IN INTEGRATED CIRCUIT PACKAGES

Abstract: Systems, apparatus, articles of manufacture, and methods to cool hotspots in integrated circuit packages are disclosed. An example apparatus includes a heat generating component associated with a first location in a semiconductor die and a heatsink assembly at a second location in the semiconductor ...

20250261406. INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS CONTINUOUS WITH GATE CUT PLUGS

Abstract: Integrated circuit structures having fin isolation regions continuous with gate cut plugs are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires...

20250261408. LAYERED THIN FILM MATERIALS FOR TRANSISTOR CHANNELS

Abstract: A thin-film transistor has a channel region with multiple thin-film layers. The transistor has a gate at one side (e.g., at the bottom) and two source/drain contacts on the opposite side (e.g., at the top). One or more channel layers closer to the gate (e.g., lower channel layers) have a higher mobi...

20250261427. INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATES AND ASSOCIATED DEFECT TEST STRUCTURES

Abstract: Integrated circuit structures having pre-spacer-deposition cut gates and associated defect test structures are described. For example, an integrated circuit structure includes a first and second fin or vertical arrangement of horizontal nanowires. First and second gate stacks are over the first and ...

20250261452. SUBSTRATE-LESS SILICON CONTROLLED RECTIFIER (SCR) INTEGRATED CIRCUIT STRUCTURES

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a se...