INTERNATIONAL BUSINESS MACHINES CORPORATION patent applications on December 19th, 2024
Patent Applications by INTERNATIONAL BUSINESS MACHINES CORPORATION on December 19th, 2024
INTERNATIONAL BUSINESS MACHINES CORPORATION: 81 patent applications
INTERNATIONAL BUSINESS MACHINES CORPORATION has applied for patents in the areas of H01L29/06 (9), H01L23/528 (9), H01L29/423 (8), H01L29/775 (8), H01L29/66 (6) H01L23/5286 (3), H01L23/481 (3), H01L23/5283 (2), G06F9/505 (2), H01L23/5223 (2)
With keywords such as: data, device, computer, based, program, gate, line, user, include, and region in patent application abstracts.
Patent Applications by INTERNATIONAL BUSINESS MACHINES CORPORATION
20240415725. WIDE SWEEP CANE_simplified_abstract_(international business machines corporation)
Inventor(s): Trudy L. Hewitt of Cary NC (US) for international business machines corporation, Mauro Marzorati of Lutz FL (US) for international business machines corporation, Carolina Garcia Delgado of Zapopan (MX) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation
IPC Code(s): A61H3/06, G01S13/60, G01S13/86
CPC Code(s): A61H3/061
Abstract: a cane for increased sweep coverage includes a first time-of-flight (tof) sensor, a haptic feedback generator and a processor. the first tof sensor is disposed at a first end of the cane and is configured to emit a first tof beam. the haptic feedback generator is disposed towards a second end of the cane that is distally opposite from the first end of the cane. the processor is configured to receive signal data from the first tof sensor, determine, based on the received signal data, whether an obstacle is present within the first tof beam, and activate the haptic feedback generator in a first haptic feedback pattern in response to the processor determining that the obstacle is present. a method for using the cane to detect obstacles is also provided.
Inventor(s): Allen Vi Cuong Chan of Markham (CA) for international business machines corporation, Sebastian Carbajales of Mississauga (CA) for international business machines corporation, Yazan Obeidi of Markham (CA) for international business machines corporation, Edward Michael Lynch of Toronto (CA) for international business machines corporation, Salman Saleem Sheikh of Sanford FL (US) for international business machines corporation, John Henry Green of Toronto (CA) for international business machines corporation, Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation
IPC Code(s): G05B13/02
CPC Code(s): G05B13/0265
Abstract: an embodiment configures a software robot to operate collaboratively with a plurality of platforms within a work environment. the embodiment decomposes, via the software robot, a request to perform a task received from one of the platforms, into at least one integration-action pair. an integration in this pair represents a configuration to operate on an execution platform within the plurality of platforms where a function is to be executed; an action in the pair represents the function to be performed on the execution platform. responsive to the determination that the at least one integration-action pair does not exist in a database of integration-action pairs, the embodiment trains the software robot to perform the function on the platform.
Inventor(s): Jill S. Dhillon of Jupiter FL (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G05B23/02
CPC Code(s): G05B23/0283
Abstract: a computer-implemented method, system, and computer program product to create optimized maintenance plans to reduce machine downtime for iot machine. the method may include determining one or more sets of minimum functionalities required to perform an activity. the method may also include determining machines capable of supporting the one or more sets of minimum functionalities. the method may also include determining a minimal level of maintenance for the machines. the method may also include generating a maintenance plan for one or more of the machines based on the minimal level of maintenance for the machines.
Inventor(s): Gil Sharon of Haifa (IL) for international business machines corporation, Nir Rozenbaum of Yoqneam Illit (IL) for international business machines corporation
IPC Code(s): G05D1/10, B64U80/00
CPC Code(s): G05D1/104
Abstract: according to one embodiment, a method, computer system, and computer program product for rescuing a malfunctioning drone is provided. the present invention may include responsive to detecting a total failure in a malfunctioning drone comprising a drone fleet, operating one or more rescue drones to physically or virtually attach to the malfunctioning drone; reconfiguring sub-missions comprising a mission assigned to the drone fleet based on an absence of the malfunctioning drone and the one or more rescue drones; and transporting, by the one or more rescue drones, the malfunctioning drone to a safe landing location.
Inventor(s): Derrick LIU of White Plains NY (US) for international business machines corporation, Ankur AGRAWAL of Chappaqua NY (US) for international business machines corporation, Chi-Chun LIU of Altamont NY (US) for international business machines corporation, Shyam RAMJI of LaGrange NY (US) for international business machines corporation, Naigang WANG of Ossining NY (US) for international business machines corporation
IPC Code(s): G06F7/499
CPC Code(s): G06F7/49915
Abstract: various embodiments are provided herein for performing a mathematical calculation in a computing environment. a quantization scheme is implemented, allowing at most one (1) non-zero-valued bit in the mantissa of a floating point number.
Inventor(s): Dinesh Kumar of Poughkeepsie NY (US) for international business machines corporation, Colleen Ann Weller of Wappingers Falls NY (US) for international business machines corporation, Margaret Annabelle Allen of Jericho VT (US) for international business machines corporation, Addison Daniel Ferrari of New Paltz NY (US) for international business machines corporation, Gary A. Van Huben of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): G06F8/41
CPC Code(s): G06F8/4432
Abstract: according to a technique of code development, a plurality of subsystem power profiles for a corresponding plurality of subsystems of a host platform in a production data processing environment are received. each of the subsystem power profiles specifies power consumption of a corresponding one of the plurality of subsystems across a range of workload traffic intensities. based on the plurality of power profiles, source code and/or software architecture of the source code is power-optimized in a development data processing environment such that, in the production data processing environment, power consumption per unit of performance of an executable program derived from the source code is improved.
Inventor(s): Si Yu CHEN of Beijing (CN) for international business machines corporation, Xiao Ling Chen of Beijing (CN) for international business machines corporation, Juliet CANDEE of Brewster NY (US) for international business machines corporation, Hao WU of Beijing (CN) for international business machines corporation
IPC Code(s): G06F8/61, G06F8/41
CPC Code(s): G06F8/63
Abstract: methods, computer program products, and systems are presented. the method computer program products, and systems can include, for instance: examining image layers of a container image and generating, in dependence on the examining, layer dependency relationship data that specifies layer dependency relationships of the container image; storing in a container repository the layer dependency relationship data that specifies layer dependency relationships of the container image; in response to receipt of a download request that specifies a targeted layer of the container image, analyzing relationship data of the layer dependency relationship data; in dependence on the analyzing, identifying a subset of image layers of the container image preceding the targeted layer; and establishing a deployment container image in dependence on the identified subset of image layers.
Inventor(s): Scott Miller of Meadville PA (US) for international business machines corporation, Joseph Evan Dunn of Tucson AZ (US) for international business machines corporation
IPC Code(s): G06F8/65
CPC Code(s): G06F8/65
Abstract: a computer-implemented method, according to one embodiment, includes collecting information from a storage cluster associated with pod deletion candidacy, and selecting a pod for deletion based on pod priorities determined using the collected information. the method further includes marking a node associated with the selected pod as not schedulable, draining the node of application workloads, and deleting the selected pod. the selected pod is recreated with a new configuration and the recreated pod is updated with updated storage software. the method further includes marking the node as schedulable. a computer program product, according to another embodiment, includes a computer readable storage medium having program instructions embodied therewith. the program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.
Inventor(s): Dong Chen of Beijing (CN) for international business machines corporation, Ye Chuan Wang of Beijing (CN) for international business machines corporation, Xiang Wei Li of Beijing (CN) for international business machines corporation, Ju Ling Liu of Beijing (CN) for international business machines corporation, Yu An of Beijing (CN) for international business machines corporation, Wei Yan of Beijing (CN) for international business machines corporation, Ting Ting Zhan of Beijing (CN) for international business machines corporation
IPC Code(s): G06F9/451, G06F3/04845
CPC Code(s): G06F9/453
Abstract: disability-related information of a user of a computing device can be acquired, the computing device can present a scene with user interface elements to the user. an accessibility requirement of the user can be identified based on the acquired disability-related information of the user. a processing routine can be determined from a plurality of processing routines stored in a routine library based on the accessibility requirement of the user. one or more of the user interface elements of the scene can be modified using the determined processing routine. the scene with the modified one or more of the user interface elements can be presented to the user through the computing device.
Inventor(s): Aladin Djuhera of Dachau (DE) for international business machines corporation, Alecio Pedro Delazari Binotto of Munich (DE) for international business machines corporation, Fernando Luiz Koch of Greenwich CT (US) for international business machines corporation, Nathalie Baracaldo Angel of San Jose CA (US) for international business machines corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5033
Abstract: the present disclosure relates to a method for executing an artificial intelligence model, including receiving an input for execution of the ai model. an input block of the ai model can be executed by a first computer system using the received input, producing a first output. the first output can be encoded. the encoded first output can be sent to a second computer system. the second computer system can decode the encoded first output. the second computer system can execute an intermediate block of the ai model using the first output, producing a second output. the second output can be encoded. the encoded second output can be sent to the first computer system. the first computer system can decode the encoded second output. the first computer system can execute an output block of the ml model using as input the second output, producing a result output.
Inventor(s): Kaustabha Ray of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F9/50, G06F9/445, G06N7/01
CPC Code(s): G06F9/505
Abstract: provided are a method, system, and computer program product in which a plurality of edge computing nodes are provided in a multi-access edge computing environment. workload allocation policies are recommended in the multi-access edge computing environment by determining which policy to use to allocate workloads to edge sites to maximize the probability of carbon footprint requirements being satisfied given the uncertainty with observability data.
Inventor(s): Guang Han Sui of Beijing (CN) for international business machines corporation, Mai Zeng of Shi Jing Shan (CN) for international business machines corporation, Min Cheng of Beijing (CN) for international business machines corporation, Peng Hui Jiang of Beijing (CN) for international business machines corporation
IPC Code(s): G06F9/50, G06F16/23
CPC Code(s): G06F9/505
Abstract: in an approach for intelligent workload scheduling, a processor groups a plurality of batch jobs based on workload resource requests and dependencies of each batch job resulting in a plurality of groups. a processor schedules the plurality of batch jobs based on the plurality of groups. a processor monitors workload resource usage of system for running the plurality of batch jobs and a plurality of transaction workloads. a processor identifies one or more scheduled transaction workloads will not be able to be completed in under a preset time threshold. a processor reduces a resource quota of one or more batch jobs of the plurality of batch jobs based on type of resource that is needed for the one or more scheduled transaction workloads.
Inventor(s): Arunava Majumdar of CHICAGO IL (US) for international business machines corporation, Monjita Sharma of Bangalore (IN) for international business machines corporation, Jeff McNeely of Princeton TX (US) for international business machines corporation, Laura Smith of Dallas TX (US) for international business machines corporation
IPC Code(s): G06F9/54, G06F11/34
CPC Code(s): G06F9/546
Abstract: an example operation may include one or more of sending messages from a host system to one or more target systems at a constant rate, wherein the processor is configured to load the messages from one or more source systems, determining that a performance of the host system, network or other system parameters has changed, maintaining the constant rate of messages from the host system to the one or more target systems based on the determination, and dynamically modifying one or more loading threads of the host system to maintain the constant rate.
Inventor(s): Kaustabha Ray of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/076
Abstract: a method, computer program product, and computer system for proactive microservice migration prior to server failure. a directed acyclic graph representing a microservice-based application and including nodes representing microservices is received. multiple execution paths passing through the nodes are identified. multiple unique servers configured to provide the microservices are identified. a continuous time markov chain model generated for each unique server is characterized by a failure rate and a repair rate of each unique server. a weight is computed for each unique server. a failure probability of each execution path is computed in dependence on the weight, and both failure and repair rate, of the unique servers. one or more vulnerable paths are selected from the multiple execution paths, wherein the failure probability of each selected vulnerable path exceeds a specified failure probability threshold. all microservices on at least one vulnerable path are migrated to one or more other servers.
Inventor(s): Madhusmita Patil of Hyderabad (IN) for international business machines corporation, Harish Bharti of Pune (IN) for international business machines corporation, Siddhartha Sood of Ghaziabad (IN) for international business machines corporation, Shweta Vohra of Farnborough (GB) for international business machines corporation
IPC Code(s): G06F12/0815
CPC Code(s): G06F12/0815
Abstract: managing data element caching is provided. non-functional requirements of a system running an application are mapped to resource utilization and system performance metric values corresponding to each of a plurality of caching parameters for each of data elements corresponding to the application suitable for caching. a caching decision is generated for each of the data elements corresponding to the application suitable for caching by identifying certain ones of the data elements for the caching to improve at least one of performance and throughput of the system based on the mapping. a data element caching decision recommendation is generated for the application based on the caching decision. the data element caching decision recommendation corresponding to the application is output to a client device of a customer via a network.
Inventor(s): Gabriel Zvi BenHanokh of Tel Aviv (IL) for international business machines corporation, Yuval Lifshitz of Kfar HaOranim (IL) for international business machines corporation
IPC Code(s): G06F12/1027, G06F12/02
CPC Code(s): G06F12/1027
Abstract: a computer-implemented method, according to one embodiment, includes generating a translation table. the translation table associates a plurality of attribute name strings with unique integer values. the method further includes outputting information about the translation table to client devices. in response to receiving, from a first of the client devices, a first request that includes a first of the unique integer values, a reply message is generated based on the first unique integer value. the reply message is output to the first client device. a computer program product, according to another embodiment, includes a computer readable storage medium having program instructions embodied therewith. the program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method.
Inventor(s): Reinhold Geiselhart of Rottenburg-Ergenzingen (DE) for international business machines corporation, Max Fabian Gilbert of Ludwigshafen am Rhein (DE) for international business machines corporation, Felix Beier of Haigerloch (DE) for international business machines corporation, Knut Stolze of Hummelshain (DE) for international business machines corporation
IPC Code(s): G06F16/22, G06F16/27
CPC Code(s): G06F16/2219
Abstract: a method for storing data in a table of a database system is disclosed. the table comprises a first column and a second column. the first column is configured for comprising first type data. the second column is configured for comprising second type data, wherein the second type data has a maximum size higher than a maximum size of the first type data. the method comprises: receiving a query to store a record in the table. it may be determined whether the record comprises a value of the second column. in case the record comprises the value of the second column, the value may be stored in a version control system and a reference token representing the value may be stored in the second column of the table. in case the record does not comprise the value of the second column, the record may be stored in the table.
Inventor(s): Reinhold Geiselhart of Rottenburg-Ergenzingen (DE) for international business machines corporation, Felix Beier of Haigerloch (DE) for international business machines corporation, Max Fabian Gilbert of Ludwigshafen am Rhein (DE) for international business machines corporation, Knut Stolze of Hummelshain (DE) for international business machines corporation
IPC Code(s): G06F16/22, G06F16/2455
CPC Code(s): G06F16/2282
Abstract: the present disclosure relates to a method for executing a query against a table of a database system, the table being configured to comprise records. the record comprises values of a set of columns, wherein one or more changes are being applied to the table in order to be synchronized with a corresponding table. the method comprises: receiving a query against the table, the query referencing one or more columns of the set of columns. it may be determined whether the application of one or more changes involving the one or more columns is completed. in response to determining that said one or more changes are applied, the query may be executed.
Inventor(s): Devbrat SHARMA of Bangalore (IN) for international business machines corporation, Soma Shekar NAGANNA of Bangalore (IN) for international business machines corporation, Abhishek SETH of Deoband (IN) for international business machines corporation, Neeraj Ramkrishna SINGH of Bangalore (IN) for international business machines corporation, Muhammed Abdul Majeed AMEEN of Kozhikode (IN) for international business machines corporation
IPC Code(s): G06F16/28, G06F16/215
CPC Code(s): G06F16/285
Abstract: one or more trained embedding generation artificial intelligence models are executed to generate a plurality of record attribute embeddings. the plurality of record attribute embeddings represents a plurality of attributes of data of a plurality of records. grouping of the plurality of record attribute embeddings is performed. the grouping of a record attribute embedding includes grouping attribute values of the record attribute embedding into one or more groups of attribute values. the performing grouping provides a plurality of groups of attribute values for the plurality of record attribute embeddings. selected records are compared to provide a set of matched records. the comparing, based on a group of attribute values, includes comparing records that include one or more attribute values grouped in the group of attribute values providing a subset of matched records of the set of matched records. the set of matched records is stored in an accessible computer location.
Inventor(s): Pankaj Dhoolia of Ghaziabad (IN) for international business machines corporation, Muhtar Burak Akbulut of Waban MA (US) for international business machines corporation, Sachindra Joshi of Gurgaon (IN) for international business machines corporation, Arnesh Batlaw of New York NY (US) for international business machines corporation, David Amid of Modiin (IL) for international business machines corporation, Tom Roach of Cambridge (GB) for international business machines corporation, Andy James Stoneberg of Clarksburg MD (US) for international business machines corporation, Dan O'Connor of Milton MA (US) for international business machines corporation, Venkat Raghavan Ganesh Sekar of Lowell MA (US) for international business machines corporation, Robert Leslie Yates of Arlington (GB) for international business machines corporation, James William Murdock, IV of Amawalk NY (US) for international business machines corporation
IPC Code(s): G06F16/332
CPC Code(s): G06F16/3329
Abstract: a computer-implemented method comprises generating an event from a task demonstration within a digital channel, forming a collaboration context based on the event, defining a collaboration by associating an assistive action with the collaboration context, transforming the collaboration context into a conversational model, evaluating an interaction session within the digital channel for an interaction that matches the collaboration context, and upon detection of the interaction that matches the collaboration context, providing the assistive action corresponding to collaboration context.
Inventor(s): Dominic Rossillo of Highland NY (US) for international business machines corporation, Michael Terrence Cohoon of Fishkill NY (US) for international business machines corporation, STEVEN LAFALCE of Salt Point NY (US) for international business machines corporation, James A. O'Connor of Ulster Park NY (US) for international business machines corporation
IPC Code(s): G06F16/33
CPC Code(s): G06F16/3335
Abstract: in an approach, a processor preprocesses a corpus of documents of a given subject matter by: scanning each document in the corpus to identify stop words, which either is a high occurrence word that appears in at least a first pre-set threshold number of documents or a low occurrence word that appears in less than a second pre-set threshold number of documents; adding the stop words to a list of stop words; performing a spellcheck function on the corpus of documents; scanning each document in the corpus to identify subject matter relevant words based on the given subject matter; adding the identified smr words to a list of smr words; and assigning a weight to each identified smr word based on a term frequency. a processor performs a similarity assessment on the corpus using the list of stop words and the list of smr words with associated weights.
Inventor(s): Michele Crudele of Rome (IT) for international business machines corporation, Luca Ioffredo of Pozzuoli (IT) for international business machines corporation, Francesca De Cicco of Rome (IT) for international business machines corporation, Fabio Monopoli of Rome (IT) for international business machines corporation
IPC Code(s): G06F16/908
CPC Code(s): G06F16/908
Abstract: disclosed embodiments provide techniques for dynamic computer log storage. log data is obtained, and templates are created from the log data. a parameter count is identified, and a score for each log line is computed, based on the parameter count, and/or additional information, such as the novelty and/or the throughput rate of the log line. each log line is scored, and based on the score, a storage strategy is applied to the log line. when scoring indicates a potentially important log line, log lines that temporally preceded and followed that log line are saved in short-term log storage, so they can be reviewed in the event that troubleshooting is needed. in this way, the cost of long-term storage for log files can be reduced considerably, while still preserving important information that is useful for maintenance, troubleshooting, and operation of deployed devices and/or software applications and systems.
Inventor(s): Alexander Brooks of Denver CO (US) for international business machines corporation, ChunHui Y. Higgins of Raleigh NC (US) for international business machines corporation, Gabriel Goodhart of Denver CO (US) for international business machines corporation, William Patrick Higgins of Durham NC (US) for international business machines corporation
IPC Code(s): G06F16/9535
CPC Code(s): G06F16/9535
Abstract: a method, computer system, and a computer program product for personalized content generation. exemplary embodiments may include receiving content and a desired personality from which to personalize the content, as well as applying the desired personality to the content via application of a personalization model to the content.
Inventor(s): William JONES of Monroe NY (US) for international business machines corporation, Tyler Vezio RIMALDI of Mahopac NY (US) for international business machines corporation
IPC Code(s): G06F17/16
CPC Code(s): G06F17/16
Abstract: method and apparatus for improved machine learning transformation operations on interleaved data are provided. a first interleaved data tensor having an unrealized set of dimensions is received, and a transformation operation to apply to the first interleaved data tensor is determined. a realized set of dimensions for output of the transformation operation is determined based on the unrealized set of dimensions and the transformation operation. a second interleaved data tensor is generated by applying the transformation operation to the first interleaved data tensor, comprising copying input elements in the first interleaved data tensor to output elements in the second interleaved data tensor based on indices in the realized set of dimensions.
Inventor(s): Vijay Ekambaram of Chennai (IN) for international business machines corporation, Arindam Jati of Bengaluru (IN) for international business machines corporation, Padmanabha Venkatagiri Seshadri of Mysore (IN) for international business machines corporation
IPC Code(s): G06F17/40, G06F17/15
CPC Code(s): G06F17/40
Abstract: systems and methods for lightweight proxy virtualization of a plurality of sensor data streams in a device are described. a processor can receive a plurality of sensor data streams from a plurality of sensors. the processor can identify missing sensor data in a sensor data stream among the plurality of sensor data streams. the processor can predict a value of the missing sensor data by running a machine learning model trained using sensor data determined based on at least one of a plurality of co-existence probabilities of the plurality of sensor data streams and a plurality of co-prediction accuracies of the plurality of sensor data streams.
Inventor(s): Johnny Shieh of Austin TX (US) for international business machines corporation, Jessica Murillo of Round Rock TX (US) for international business machines corporation, Kelley Anders of East New Market MD (US) for international business machines corporation
IPC Code(s): G06F21/46
CPC Code(s): G06F21/46
Abstract: computer generated password criteria generated in response to a required password change can include detecting a request for a new password for a program. a password criteria for the new password is generated, which is different than a previous password criteria. a submitted new password is received and a determination is made when the submitted new password meets each of the password criteria for the new password. responsive to determining the submitted new password meets each of the password criteria for the new password, access is allowed to the program.
Inventor(s): Bradley Donald Bingham of Austin TX (US) for international business machines corporation, Jason Raymond Baumgartner of Austin TX (US) for international business machines corporation, Viresh Paruthi of Austin TX (US) for international business machines corporation
IPC Code(s): G06F30/33
CPC Code(s): G06F30/33
Abstract: a computer-implemented method, system, and computer program product for applying scalable formal coverage analysis to a testbench. a set of properties proven unhittable in an original testbench is selected to be considered for coverage analysis. a gate (e.g., latch) of a device under test is selected and mutated, where the mutation includes utilizing a random value and where a mutation property for the set of selected properties proven unhittable is associated with the mutated gate of the device under test. it is then determined whether the mutation property is hittable or unhittable while the gate is mutated in order to determine whether the gate is covered by the selected properties. a gate is covered by the selected properties if the mutation property is hittable while the gate is mutated. furthermore, a gate is uncovered by the selected properties if the mutation property is unhittable while the gate is mutated.
Inventor(s): Xiaoming Yang of Clifton Park NY (US) for international business machines corporation, SOMNATH GHOSH of Clifton Park NY (US) for international business machines corporation, Huai Huang of Clifton Park NY (US) for international business machines corporation, Yann Mignot of Slingerlands NY (US) for international business machines corporation, Kai Zhao of Albany NY (US) for international business machines corporation, Daniel Charles Edelstein of White Plains NY (US) for international business machines corporation
IPC Code(s): G06F30/39
CPC Code(s): G06F30/39
Abstract: embodiments of the invention are directed to a computer system having a processor communicatively coupled to a memory. the processor performs processor operations that include accessing an electronic file that includes an electronic integrated circuit (ic) design. the electronic file is operable to control a fabrication system to fabricate an ic according to the electronic ic design. the processor operations further includes applying a bulging predication analysis to the electronic ic design; and making one or more changes to the electronic ic design based at least in part on a result of the bulging prediction analysis.
Inventor(s): Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation, Jonathan D. Dunne of Dungarvan (IE) for international business machines corporation, Norton Samuel Augustus Stanley of Bangalore (IN) for international business machines corporation, Hemant Kumar Sivaswamy of Pune (IN) for international business machines corporation
IPC Code(s): G06F40/151, G06F40/166, G06F40/20
CPC Code(s): G06F40/151
Abstract: the illustrative embodiments provide for signature discourse transformation. an embodiment includes detecting a signature discourse of a user by analyzing the user's discourse using corpus linguistics. the embodiment also includes generating computing a collection of words distinct to the user. the embodiment also includes sensing, using tone analysis and a natural language process model, a tone of the collection of words distinct to the user in the signature discourse utterance. the embodiment also includes mapping a cartesian value of the collection of words distinct to the user. the embodiment also includes deriving a signature discourse transformation (sdt) model from the signature discourse utterances, the collection of words, the tone, and the cartesian value. the embodiment also includes transforming, using the signature discourse transformation, an original discourse by the user into an anonymized text.
20240419924. Full Media Translator_simplified_abstract_(international business machines corporation)
Inventor(s): Daniel Ajagbusi of Brooklyn Park MN (US) for international business machines corporation
IPC Code(s): G06F40/58, G06F40/205, G06F40/242, G06F40/51, G06V30/10
CPC Code(s): G06F40/58
Abstract: a computer implemented method for translating a document. a number of processor units separate the document into elements having media types. the number of processor units determine attributes for the elements. the number of processor units create a virtual map identifying relationships between the elements using the attributes. the number of processor units translate the elements into a target language based on media types for the elements. the number of processor units adjust translations for the elements based on the relationships between the elements using the virtual map to create adjusted translations for the elements. the number of processor units generate the translated document using the adjusted translations for the elements and the virtual map.
Inventor(s): Sebastien Gilbert of Granby (CA) for international business machines corporation
IPC Code(s): G06N3/0464
CPC Code(s): G06N3/0464
Abstract: a system may allocate, in response to receiving an input tensor of a predetermined shape, a portion of convolution kernels to a predetermined number of spatial frequency bands; replace the convolution layer in a convolutional neural network with a sequence of band splitting, parallel convolutions, and concatenation; and form, in response to completing stages for the predetermined number of spatial frequency bands, a final output tensor.
Inventor(s): AMEET DESHPANDE of PRINCETON NJ (US) for international business machines corporation, ANTHONY FERRITTO of NEW YORK NY (US) for international business machines corporation, AVIRUP SIL of HOPEWELL JUNCTION NY (US) for international business machines corporation, MD ARAFAT SULTAN of CROTON-ON-HUDSON NY (US) for international business machines corporation
IPC Code(s): G06N3/08, G06N3/045
CPC Code(s): G06N3/08
Abstract: techniques for incremental domain adaptation are provided using iterative knowledge distillation to sequentially adapt a machine learning model to new tasks, and an external memory bank for storing the machine learning model parameters pertaining to the new tasks. in one aspect, a system for incremental domain adaptation includes: an iterative knowledge distillation module configured to adapt machine learning models to new tasks sequentially through multiple iterations of knowledge distillation; and an external memory bank configured to store parameters of the machine learning models pertaining to the new tasks. the external memory bank can employ adaptive memory allocation. a method for incremental domain adaptation using the present system is also provided.
Inventor(s): Julian Röttger Büchel of Zurich (CH) for international business machines corporation, Manuel Le Gallo-Bourdeau of Horgen (CH) for international business machines corporation, Abu Sebastian of Adliswil (CH) for international business machines corporation
IPC Code(s): G06N3/084
CPC Code(s): G06N3/084
Abstract: precision of a neural processing apparatus comprising two in-memory compute (imc) units is controlled, wherein the imc units include a first imc unit and a second imc unit, each designed to perform vector-matrix multiplication (vmm) to produce analog output signals. an artificial neural network (ann) model is trained to learn its parameters (including synaptic weight values) in accordance with a dual objective. the ann model comprises two neural layers, these including a first neural layer and a second neural layer. the method further comprises storing the synaptic weight values of the parameters learned in the two imc units to respectively map the first neural layer and the second neural layer onto the first imc unit and the second imc unit. the second imc unit is designed to perform vmm operations based on analog input signals generated from activation values produced by the first neural layer.
Inventor(s): Marco Luca Sbodio of Dublin (IE) for international business machines corporation, Natalia Mulligan of Dublin (IE) for international business machines corporation, Joao H. Bettencourt-Silva of Dublin (IE) for international business machines corporation
IPC Code(s): G06N5/04
CPC Code(s): G06N5/04
Abstract: accuracy evaluation of concept expansion systems is provided. a returned set of related concepts corresponding to a test set of concepts is received from a concept expansion system. a comparison is performed between an expected set of concepts and the returned set of related concepts corresponding to the test set of concepts to identify intersection. an accuracy metric corresponding to the concept expansion system is generated based on the intersection between the expected set of concepts and the returned set of related concepts corresponding to the test set of concepts. it is determined whether the accuracy metric is greater than a minimum accuracy threshold level. a set of action steps is performed in response to determining that the accuracy metric is not greater than the minimum accuracy threshold level.
Inventor(s): Jun Su of Beijing (CN) for international business machines corporation, YANG LIANG of Beijing (CN) for international business machines corporation, Su Liu of Austin TX (US) for international business machines corporation, James Nash of Lewisville TX (US) for international business machines corporation
IPC Code(s): G06N5/04
CPC Code(s): G06N5/04
Abstract: provided are a computer program product, system, and method for validating answers from an artificial intelligence chatbot. an answer is received to a question submitted to the artificial intelligence chatbot. a database is searched using keywords from the answer to obtain a reference for the answer. a similarity score is calculated between the answer and the reference. a determination is made as to whether the similarity score exceeds a threshold value. answer information indicates that the answer is valid in response to the similarity score exceeding the threshold value or that the answer is invalid in response to the similarity score not exceeding the threshold value. an answer report indicating whether the answer is valid or invalid to transmit to a user a user that submitted the question to render.
Inventor(s): MUIR KUMPH of Croton on Hudson NY (US) for international business machines corporation, JOHN BLAIR of Katonah NY (US) for international business machines corporation
IPC Code(s): G06N10/40, H01P1/38
CPC Code(s): G06N10/40
Abstract: one or more systems, devices and/or computer-implemented methods of use provided herein relate to single-device readout of the state of a coupler qubit and flux control of that coupler qubit, which processes can be performed simultaneously. in one or more embodiments, an electronic system comprises a coupler qubit, a pair of superconducting qubits coupled to the coupler qubit, a multiplexed input line, and a readout and flux control subsystem coupled between the multiplexed input line and the coupler qubit, wherein the readout and flux control subsystem is configured to allow for both readout of a state of the coupler qubit and flux control that adjusts a coupling between the pair of superconducting qubits. the diplexer couples together the readout resonator and a flux control portion of the electronic system, wherein the readout resonator and the flux control portion are separated from one another between the diplexer and the coupler qubit.
Inventor(s): Michael KATZ of Goldens Bridge NY (US) for international business machines corporation, Junkyu LEE of San Diego CA (US) for international business machines corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: computer implemented methods, systems, and computer program products include program code executing on a processor(s) that obtains a planning problem and one or more bounding conditions for the solutions. the program code transforms the planning problem into a single-goal form. the program code computes stubborn sets over the single-goal form of the planning problem. the program code defines a pruned search space utilizing the single-goal form of the planning problem and the stubborn sets. the program code performs a k* search over the pruned search space. the program code obtains the set of solutions.
Inventor(s): Michael KATZ of Goldens Bridge NY (US) for international business machines corporation, Junkyu LEE of San Diego CA (US) for international business machines corporation
IPC Code(s): G06Q10/04
CPC Code(s): G06Q10/04
Abstract: computer implemented methods, systems, and computer program products include program code executing on a processor(s) that obtains a planning problem. the program code obtains a bound on a number of plans (to address the planning problem). the program code identifies symmetries of the planning problem. the program code utilizes the symmetries to identify an orbit search space of the planning problem. the program code executes a two-phase search iteratively over the orbit space to identify surrogate plans in the orbit space. the program code generates new plans by utilizing the surrogate plans and the symmetries of the planning problem to map the surrogate plans to new plans. the program code extends the new plans. the extended new plans comprise the set of solutions for the planning problem.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Mallanagouda B Patil of Bangalore (IN) for international business machines corporation, Shailendra Moyal of Pune (IN) for international business machines corporation
IPC Code(s): G06Q10/10, G06Q50/00
CPC Code(s): G06Q10/103
Abstract: techniques are described with respect to a system, method, and computer product for a method for sharing virtual environment collaboration. an associated method includes analyzing a virtual environment and determining a plurality of contextual information and a degree of shareability associated with the virtual environment based on the analysis. the method further including presenting the virtual environment to a social media network associated with a user based on the degree of shareability.
Inventor(s): Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation, Melanie Dauber of Oceanside NY (US) for international business machines corporation, Jacob Ryan Jepperson of St. Paul MN (US) for international business machines corporation, Spencer Thomas Reynolds of Austin TX (US) for international business machines corporation, Logan Bailey of Atlanta GA (US) for international business machines corporation
IPC Code(s): G06Q10/10, G10L15/18, G10L15/22
CPC Code(s): G06Q10/103
Abstract: disclosed embodiments provide for a computer-implemented method. the method includes obtaining text data pertaining to a project. natural language processing (nlp) is performed on the obtained text data, which includes detecting one or more entities. sentiment analysis associated with the detected one or more entities is performed. an automated project adjustment is performed based on the performed sentiment analysis and the detected one or more entities.
Inventor(s): Wesley Ip of Arlington TX (US) for international business machines corporation, Logan Bailey of Atlanta GA (US) for international business machines corporation, Alexandra M. Isaly of Lighthouse Point FL (US) for international business machines corporation, RYAN Michael SPARKS of Norman OK (US) for international business machines corporation, Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation
IPC Code(s): G06Q30/0601, G06T19/00
CPC Code(s): G06Q30/0631
Abstract: according to one embodiment, a method, computer system, and computer program product for managing a physical storage system of a user is provided. the present invention may include identifying a physical item that a user has selected for acquisition; selecting one or more storage areas of a plurality of storage areas comprising the physical storage system to store the item in based on a category associated with the item; determining an amount of storage space required to store the item based on dimensions of the item; comparing the determined amount of storage space against a current amount of free storage space within the one or more selected storage areas; and responsive to identifying that the determined amount of storage space exceeds the current amount of free space based on the comparing, generating an alert to the user.
Inventor(s): Kai Zhang of Thornhill (CA) for international business machines corporation, Xiaoying Gao of San Jose CA (US) for international business machines corporation, Rajesh M. Desai of San Jose CA (US) for international business machines corporation, Sudhakar Basireddy of San Jose CA (US) for international business machines corporation
IPC Code(s): G06T7/00, G06T7/73, G06V10/764, G06V10/77, G06V10/774, G06V30/19, G06V30/413
CPC Code(s): G06T7/0002
Abstract: mechanisms are provided for automated document image annotation and data extraction. a received document image is processed to identify a document type of the received document image, and retrieve a corresponding document template having key point location data and annotation location data for documents of the document type. first key points of the received document image are matched with second key points of the corresponding document template and a mapping is generated to map locations of the document template to locations of the received document image. a perspective transformation is applied, based on the mapping, to first annotation locations specified in the document template data structure to generate second annotation locations corresponding to locations in the received document image. data extraction is performed on data associated with the second annotation locations based on the annotations corresponding to the second annotation locations.
Inventor(s): Beth Karos of Valencia PA (US) for international business machines corporation, Kelley Anders of East New Market MD (US) for international business machines corporation
IPC Code(s): G06T19/00, G06V10/74
CPC Code(s): G06T19/006
Abstract: techniques are described with respect to a system, method, and computer program product for visualizing optimal augmented reality (ar) assistance. an associated method includes receiving a plurality of object data of at least one object associated with a user; generating an optimal assistance model based on analysis of the plurality of object data; predicting a plurality of object metrics of the object based on the optimal assistance model; and visualizing the plurality of object metrics in a virtual environment associated the user.
Inventor(s): Pin-Yu Chen of White Plains NY (US) for international business machines corporation, I-Hsin Chung of Chappaqua NY (US) for international business machines corporation, Bo Wu of Cambridge MA (US) for international business machines corporation, Chuang Gan of Cambridge MA (US) for international business machines corporation, Tsung-Yi Ho of Hsinchu (TW) for international business machines corporation, Sheng-Yen Chou of Tainan City (TW) for international business machines corporation
IPC Code(s): G06V10/774
CPC Code(s): G06V10/774
Abstract: techniques regarding generating a synthetic dataset of objects are provided. for example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. the system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. the computer executable components can include a defining component that can define a tractable forward process associated with a diffusion model, with defining the tractable forward process including inputting noise to compromise training data, resulting in compromised training data. the computer executable components can further include a training component that, using the compromised training data, trains the diffusion model to reverse process the tractable forward process, wherein the training results in a compromised diffusion model.
Inventor(s): Tushar Agrawal of West Fargo ND (US) for international business machines corporation, ChunHui Y. Higgins of Raleigh NC (US) for international business machines corporation, Pengxiang Xu of Huntington Beach CA (US) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06V20/52, G06T7/80, G06V10/82, G06V20/70, G10L21/0208
CPC Code(s): G06V20/52
Abstract: techniques are described with regard to automatic machine configuration in a workspace environment. an associated computer-implemented method includes collecting workspace activity data in a workspace environment including at least one machine, wherein the workspace activity data is collected at least in part via a plurality of video frames captured by a plurality of video cameras and via a plurality of audio segments captured by at least one microphone. the method further includes configuring at least one workspace positioning artificial neural network based upon analysis of the workspace activity data, applying the at least one workspace positioning artificial neural network to derive at least one human activity datapoint in the workspace environment, and automatically configuring the at least one machine based upon the at least one human activity datapoint.
Inventor(s): Hyman David Chantz of Scarsdale NY (US) for international business machines corporation, Pascal R. Bastien of Poughkeepsie NY (US) for international business machines corporation, David Horsfield of New York NY (US) for international business machines corporation, Justin Rosenthal of Hewlett Harbor NY (US) for international business machines corporation
IPC Code(s): G07C5/00, G08G1/00
CPC Code(s): G07C5/008
Abstract: computer-implemented methods for a vehicle-generated data management system. aspects include receiving vehicle-generated data from a vehicle associated with a vehicle-generated data management system. aspects further include processing the vehicle-generated data to extract sensor data, gps data, and time data. aspects further include generating situational data using the sensor data, the gps data and the time data. aspects further include transmitting the situational data and the processed vehicle-generated to a hybrid cloud system.
Inventor(s): Yang Du of San Jose CA (US) for international business machines corporation, Andrew Low of Stittsville (CA) for international business machines corporation, Jennifer Mulsow of Cedar Park TX (US) for international business machines corporation
IPC Code(s): G09B7/02, G06N5/02
CPC Code(s): G09B7/02
Abstract: embodiments of the present invention provide an approach for applying cognitive diagnostic modeling (cdm) and deep learning algorithms to improve knowledge transfer (kt) progress. specifically, the approach aims to improve the process of transferring knowledge by breaking down a learning task into smaller subtasks that are related to a specific learning goal. the provided responses for each subtask are then evaluated using a deep learning algorithm, which generates a continuous score based on the difference between the provided response and the expected response. each continuous score is then converted into a binary value to obtain a set of binary values. based on the set of binary values, a diagnostic report is generated that reflects the progress of knowledge transfer for the assigned learning task. this approach allows for a more detailed and accurate assessment of the learning process, which can help to identify areas where further improvement is needed.
Inventor(s): Jill S. Dhillon of Jupiter FL (US) for international business machines corporation, Jennifer M. Hatfield of Portland OR (US) for international business machines corporation, Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation
IPC Code(s): G09B21/00, G06F3/01, G06F3/16, G10L15/26
CPC Code(s): G09B21/009
Abstract: an approach for improving communications for hearing challenged individuals. the approach captures audio communication and video communication associated with a speaker presentation. the approach converts the audio communication to text. the approach sends the text to an augmented reality (ar) device, associated with a user having hearing challenges, as captions. the approach stores the audio communication, the video communication, and the captions for replay by the user.
Inventor(s): Irene Lizeth Manotas Gutiérrez of White Plains NY (US) for international business machines corporation, Ra’eesa Kabir of Birmingham (GB) for international business machines corporation, Jonathan D. Dunne of Dungarvan (IE) for international business machines corporation
IPC Code(s): G10L15/18, G10L15/22
CPC Code(s): G10L15/1815
Abstract: according to one embodiment, a method, computer system, and computer program product for human-machine interfacing is provided. the present invention may include receiving a personality corpus associated with a personality typology comprising multiple personality types; extracting a plurality of utterances from a user; selecting, by a personality model, a personality type associated with the user based on the utterances and the personality corpus; identifying a compatible personality type of the selected personality type; constructing one or more natural language scripts from a word graph associated with the compatible personality type; and transmitting the one or more natural language scripts to the user.
Inventor(s): Benedikt Kersting of Lüdinghausen (DE) for international business machines corporation, Athanasios Vasilopoulos of KIlchberg (CH) for international business machines corporation, Manuel Le Gallo-Bourdeau of Horgen (CH) for international business machines corporation, Julian Röttger Büchel of Zuerich (CH) for international business machines corporation, Abu Sebastian of Adliswil (CH) for international business machines corporation
IPC Code(s): G11C13/00, G11C11/54
CPC Code(s): G11C13/0069
Abstract: the present disclosure relates to a method for compensating non-ideality of a neuromorphic memory device. the neuromorphic memory device comprising a crossbar array of wordlines and bitlines. the crossbar array comprises a block of wordline and bitline segments, wherein memory elements of the block are programmed to represent array values. the device is configured for applying a set of inputs to the initial wordlines for performing dot products. the method comprises: performing at least one of: wordline expansion or bitline expansion of the block. the set of inputs may be applied to the initial wordlines of the expanded block and in case the bitline expansion is performed an additional input may be applied to the additional wordlines of the expanded block. the currents flowing in the bitlines of the expanded block may be measured. the dot products may be determined using the measured currents.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation
IPC Code(s): H01L21/28, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/775
CPC Code(s): H01L21/28123
Abstract: a semiconductor ic device includes an inverted gate cut region with a relatively larger bottom surface area compared to its top surface area. as a result, an associated gate structure may have a relatively larger top contact landing surface area relative to its bottom surface area. the inverted gate cut region may increase a propensity of a frontside gate contact to meld with the gate structure. the increased landing area further enables the frontside contact to be placed in further perimeter locations. the inverted gate cut region also results in improved resistance characteristics through the gate structure. specifically, the inverted gate cut region enables a wide region between a top channel and the inverted gate cut region that provides a relatively lower electrical resistance therethrough. similarly, the inverted gate cut region causes a bottom perimeter region with decreased conductive material therein which advantageously results in lower associated parasitic capacitances.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation
IPC Code(s): H01L21/28, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L21/28123
Abstract: a semiconductor ic device includes an inverted gate cut region with a relatively larger bottom surface area compared to its top surface area. as a result, an associated gate structure may have a relatively larger top contact landing surface area relative to its bottom surface area. the increased landing area further enables the frontside contact to be in further perimeter locations. the inverted gate cut region also results in improved resistance characteristics through the gate structure. specifically, the inverted gate cut region enables a wide region between a top channel and the inverted gate cut region that provides a relatively lower electrical resistance therethrough. similarly, the inverted gate cut region causes a bottom perimeter region with decreased conductive material therein which advantageously results in lower associated parasitic capacitances.
Inventor(s): Lijuan Zou of Slingerlands NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation
IPC Code(s): H01L21/762, H01L21/84, H01L27/12
CPC Code(s): H01L21/76224
Abstract: a semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors. each field effect transistor includes source/drain regions located on opposite sides of the field effect transistors. a shallow trench isolation region located between adjacent field effect transistors electrically separates the plurality of field effect transistors from one another. the shallow trench isolation region has a tapered profile. a backside isolation region is embedded within the shallow trench isolation region and cuts through the source/drain regions. the backside isolation region has a reverse tapered profile.
Inventor(s): Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Tenko Yamashita of Schenectady NY (US) for international business machines corporation
IPC Code(s): H01L21/8234, H01L21/768, H01L23/528, H01L27/088, H01L29/08
CPC Code(s): H01L21/823475
Abstract: embodiments of the present invention are directed to processing methods and resulting structures for providing contacts for gate, source, and drain regions through a wafer backside. in a non-limiting embodiment of the invention, a front end of line structure having a gate and a source or drain (s/d) region is formed and a back end of line structure is formed on a first surface of the front end of line structure. the back end of line structure includes a backside s/d contact on a surface of the s/d region, a backside gate contact on a surface of the gate, and a backside contact liner in direct contact with a sidewall of the backside s/d contact and a sidewall of the backside gate contact. the backside gate contact is electrically isolated from the backside s/d contact by the backside contact liner.
Inventor(s): Nicolas Jean Loubet of GUILDERLAND NY (US) for international business machines corporation, Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8234, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L23/481
Abstract: a microelectronic device including a nanosheet transistor that includes a first source/drain and a second source/drain. a frontside contact connected to the first source/drain and a backside contact connected to the second source/drain. a plurality of isolation layers located beneath the nanosheet transistor, and the second source/drain extends through the plurality of isolation layers to connect with the backside contact.
Inventor(s): Lijuan Zou of Slingerlands NY (US) for international business machines corporation, Shahrukh Khan of Sandy Hook CT (US) for international business machines corporation, Biswanath Senapati of Mechanicville NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8238, H01L27/092, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L23/481
Abstract: embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. a plurality of nanosheet recesses are formed within a substrate. a placeholder structure is formed on a bottom surface within each nanosheet recess. a first source/drain region is formed within a first nanosheet recess. a second source/drain region is formed within the second nanosheet recess. the semiconductor structure is flipped. the substrate is removed respective to a sidewall spacer of the placeholder structure and a first etch stop layer of the placeholder structure. backside interlayer dielectric is formed. a backside contact trench to the second source drain region is formed by removing a portion of the backside interlayer dielectric over the second source/drain region and removing exposed portions of the first etch stop layer, the sidewall spacer, and a silicon buffer layer of the placeholder structure. a backside contact is formed within the trench.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L23/522, H01L23/528
CPC Code(s): H01L23/481
Abstract: a semiconductor structure includes a stacked device structure containing a first device and a second device over the first device in a stacked configuration. the semiconductor structure further includes a first backside contact connected to the first device and a first backside power line. the semiconductor structure further includes a second backside contact connected to the second device and a second backside power line.
Inventor(s): Chanro Park of Clifton Park NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation, Ashim Dutta of Clifton Park NY (US) for international business machines corporation, Shravana Kumar Katakam of Lehi UT (US) for international business machines corporation
IPC Code(s): H01L23/522
CPC Code(s): H01L23/5223
Abstract: a semiconductor device including a metal insulator metal capacitor (mim capacitor) within back end of line circuitry, where a bottom electrode of the mim capacitor includes a plurality of vertical pillars extending up from a bottom layer. a semiconductor device including a metal insulator metal capacitor (mim capacitor), where a bottom electrode of the mim capacitor includes a plurality of vertical pillars extending up from a bottom layer. forming back end of line mx-1 metal line layer, forming a plurality of vx-1 via on the mx-1 metal line layer, forming mx metal line layer with subtractive patterning on the plurality of the vx-1 via, forming a plurality of vx via on the mx metal line layer with subtractive patterning; and forming a block mask protecting a portion of the semiconductor device.
Inventor(s): Baozhen Li of South Burlington VT (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation, HUIMEI ZHOU of Albany NY (US) for international business machines corporation, Yueming Xu of Wappingers Falls NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L23/528
CPC Code(s): H01L23/5223
Abstract: a semiconductor device including a metal insulator metal capacitor (mim capacitor) within back end of line circuitry of the semiconductor device, where the mim capacitor surrounds a first mx metal line. a semiconductor device including a metal insulator metal capacitor (mim capacitor) within back end of line circuitry of the semiconductor device, where the mim capacitor surrounds a first mx metal line, where a lower horizontal surface of the mim capacitor is vertically adjacent to an upper horizontal surface of an mx-1 metal line. a method including forming a metal insulator metal capacitor (mim capacitor) within back end of line circuitry of the semiconductor device, where the mim capacitor surrounds a first mx metal line.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: a semiconductor interconnect structure and formation thereof. the semiconductor interconnect structure includes a subtractively formed via located on top of a lower level metal line. the subtractively formed via has a bottom portion and a top portion. the semiconductor interconnect structure further includes a selectively grown region formed onto the top portion of the subtractively formed via. a portion of the selectively grown region overhangs the bottom portion of the subtractively formed via in one or more directions.
Inventor(s): Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Chih-Chao Yang of Glenmont NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/768
CPC Code(s): H01L23/528
Abstract: according to the embodiment of the present invention, a semiconductor device includes an interconnect. the interconnect includes a bottom interconnect section and a top interconnect section. the bottom interconnect section includes a first orientation along a y-axis. the top interconnect section is coupled to the bottom interconnect section and includes a second orientation along to the y-axis. the second orientation of the top interconnect section is a vertical reflection of the first orientation of the bottom interconnect section.
Inventor(s): Brent A. Anderson of Jericho VT (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/522
CPC Code(s): H01L23/5283
Abstract: a semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. the interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/48, H01L23/522
CPC Code(s): H01L23/5283
Abstract: a semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. the first type of lines have a wider top surface than the bottom surface and have a first width. the first type of lines each connect by a first via to a second backside metal level. each of first type of lines and the second type line connect by a second via to a through-silicon via. the second type line is narrower than the first type of lines. each of the second type line is between adjacent first type of lines. the second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.
Inventor(s): Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Eric Miller of Albany NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L29/06, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L23/5286
Abstract: a semiconductor structure includes a plurality of gate-all-around field effect transistors. each of the gate-all-around field effect transistors includes first and second source-drain regions; at least one channel region interconnecting the first and second source-drain regions; and a gate structure surrounding the at least one channel region. a direct backside contact is located below one of the first and second source-drain regions. the direct backside contact has an upper portion. a dielectric liner is wrapped around the upper portion of the direct backside contact.
Inventor(s): Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/775
CPC Code(s): H01L23/5286
Abstract: according to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. the second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. a first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. a first gap exists between the first backside signal line and the second backside signal line.
Inventor(s): Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Huai Huang of Clifton Park NY (US) for international business machines corporation, Hosadurga Shobha of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/528, H01L21/8238, H01L23/498, H01L23/535
CPC Code(s): H01L23/5286
Abstract: a microelectronic structure including a backside-power-distribution-network (bsdpn) connected to a backside of a device region. the bspdn includes a plurality of first type power rails and a plurality of second type power rails located on the same level. a first power plane located on a level above the plurality of first type power rails and the plurality of second type power rails. the first power plane extends across the plurality of first type power rails and the plurality of second type power rails and the first power plane is connected to a plurality of first type power rails, but not connected to the plurality of second type power rails.
Inventor(s): Eric Peter Lewandowski of White Plains NY (US) for international business machines corporation, Jae-Woong Nah of Closter NJ (US) for international business machines corporation, Dongbing Shao of Briarcliff Manor NY (US) for international business machines corporation
IPC Code(s): H01L23/00, H01L25/18, H10N60/81
CPC Code(s): H01L24/17
Abstract: systems and techniques that facilitate uniform qubit chip gaps via injection-molded solder pillars are provided. in various embodiments, a device can comprise one or more injection-molded solder interconnects. in various aspects, the one or more injection-molded solder interconnects can couple at least one qubit chip to an interposer chip. in various embodiments, the device can further comprise one or more injection-molded solder pillars. in various instances, the one or more injection-molded solder pillars can be between the at least one quit chip and the interposer chip. in various cases, the one or more injection-molded solder pillars can be in parallel with the one or more injection-molded solder interconnects. in various embodiments, the one or more injection-molded solder pillars can facilitate and/or maintain a uniform gap between the at least one qubit chip and the interposer chip. in various embodiments, a melting point of the one or more injection-molded solder pillars can be higher than a melting point of the one or more injection-molded solder interconnects. in various embodiments, the one or more injection-molded solder pillars can be superconductors. in various embodiments, a yield strength of the one or more injection-molded solder pillars can be between 3,000 pounds per square inch and 15,000 pounds per square inch, which can be higher than a yield strength of the one or more injection-molded solder interconnects. in various embodiments, the one or more injection-molded solder pillars can be binary tin alloys, tertiary tin alloys, and/or quaternary tin alloys.
Inventor(s): Carl Radens of LaGrangeville NY (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L27/02, H10B10/00
CPC Code(s): H01L27/0207
Abstract: a semiconductor structure includes a first circuit row including one or more first circuit cells and a second circuit row including one or more second circuit cells. at a cell boundary between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row, one or more first gate regions of the one or more first circuit cells in the first circuit row are staggered with one or more second gate regions of the one or more second circuit cells in the second circuit row.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Biswanath Senapati of Mechanicville NY (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Brent A. Anderson of Jericho VT (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L27/0922
Abstract: a semiconductor structure includes a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, and a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height. the second level is vertically stacked over the first level, the first gate pitch is different than the second gate pitch, and the first cell height is different than the second cell height.
Inventor(s): Jason J Stuffle of Burlington VT (US) for international business machines corporation, Albert M. Chu of Nashua NH (US) for international business machines corporation, Charles Nicholas Perez of Burlington VT (US) for international business machines corporation
IPC Code(s): H01L29/06, G11C16/34, H01L27/02, H01L27/092, H01L29/08
CPC Code(s): H01L29/0607
Abstract: a device comprises memory configured to store program instructions, and processing circuitry, coupled to the memory, and configured to execute the program instructions to perform a process to limit current leakage. the processing circuitry is configured to receive an input of an initial layout of a semiconductor structure comprising a plurality of cells, identify a plurality of edge source/drain regions in respective ones of the cells, determine respective electrical configurations for the edge source/drain regions, compute respective values associated with current leakage for adjacent cells in the initial layout and in a plurality of alternative layouts of the semiconductor structure based at least in part on the respective electrical configurations for the edge source/drain regions, and identify at least one alternative layout of the plurality of alternative layouts to the initial layout that results in at least a reduction of total current leakage from the initial layout.
Inventor(s): Shogo Mochizuki of Mechanicville NY (US) for international business machines corporation, Erin Stuckert of Albany NY (US) for international business machines corporation
IPC Code(s): H01L29/08, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0847
Abstract: a transistor includes a funneled interfacial source/drain (s/d) region that includes a narrow throat that is connected to or is an interface to the nanolayer channel. the funneled interfacial s/d region may also include a wide throat that is an interface to a remainder of the s/d region. the funneled interfacial source/drain (s/d) region may reduce parasitic resistance or impedance from the s/d region into or out of a nanolayer channel.
Inventor(s): OMPRAKASH RAMAVADH UPADHYAY of Dallas TX (US) for international business machines corporation, Mudit Mehrotra of Bengaluru (IN) for international business machines corporation
IPC Code(s): H04L9/32
CPC Code(s): H04L9/3236
Abstract: a system, method, and computer program product are configured to: receive a message at a first data center, wherein the message includes a payload and is associated with a transaction; create a correlation identifier for the message using an encryption process with the payload of the message; replicate the message and the correlation identifier at a second data center, wherein the replicated message includes a copy of the payload in a work-in-progress queue of the second data center; and in response to a failure of the first data center and a processing of the transaction using the replicated message at the second data center, reconcile the transaction using the correlation identifier.
Inventor(s): BRAULIO GABRIEL DUMBA of White Plains NY (US) for international business machines corporation, Gloire Rubambiza of Mountain View CA (US) for international business machines corporation, Andrew John Anderson of Stamford CT (US) for international business machines corporation
IPC Code(s): H04L41/0668, G16Y10/75, G16Y30/00, H04L67/568
CPC Code(s): H04L41/0668
Abstract: an edge site maintains a plurality of rendezvous nodes to which a plurality of internet of things (iot) devices are communicatively coupled, where the plurality of rendezvous nodes are also communicatively coupled to an edge hub in the edge site. a cached model is maintained at the edge hub, where the cached model enables the edge site to stay operational in an event of a failure of a cloud hub to which the edge hub is communicatively coupled.
Inventor(s): Gandhi SIVAKUMAR of Bentleigh (AU) for international business machines corporation, Tanmay Jayant MUJUMDAR of Pune (IN) for international business machines corporation, Kushal S. PATEL of Pune (IN) for international business machines corporation, Sarvesh S. PATEL of Pune (IN) for international business machines corporation
IPC Code(s): H04L47/122, H04L43/0817, H04L47/2425
CPC Code(s): H04L47/122
Abstract: condition-based, selective workload reduction through at least one port of a network device is provided. the process includes determining, by a network device of a computing environment, that the network device has a defined condition, and obtaining, by the network device, classifications of applications using the network device, where the classifications include multiple different application classifications. further, the process includes reducing, by the network device, workload through at least one port of the network device based on determining that the network device has the defined condition. the reducing includes reducing workload through the at least one port of the network device of an application of a particular application classification of the multiple different application classifications, without reducing workload through a selected port of the network device of another application of a different application classification of the multiple different application classifications.
Inventor(s): Benjamin William Shade of Waterlooville (GB) for international business machines corporation, Krithika Ramachandran of Georgetown TX (US) for international business machines corporation, Mauro Marzorati of Lutz FL (US) for international business machines corporation, Michael Guilford of Cary NC (US) for international business machines corporation
IPC Code(s): H04L9/40, H04L51/48
CPC Code(s): H04L63/0442
Abstract: original content of an email message is verified upon receipt of the email message at a receiver mail server prior to presenting the email message to a recipient. determination of original content is made by comparing a verification hash value to a calculated hash value of the received email message. when the verification hash value does not match the calculated hash value, an invalidity warning is presented to the recipient with an option to view the invalid email message.
Inventor(s): KAWEEPOJ PHACHARINTANAKUL of Warwick (GB) for international business machines corporation, Wolfgang von Drews of Crailsheim (DE) for international business machines corporation, Gwilym Benjamin Lee Newton of Winchester (GB) for international business machines corporation
IPC Code(s): H04L9/40, H04W4/021
CPC Code(s): H04L63/0838
Abstract: a computer-implemented method, a computer program product, and a computer system for using a user location as a security factor for online services. upon receiving from a computing device of a user a request for a digital service allowed in a geofence, a first computer hosting a digital service provider generates an original one-time password (otp) and sends the original otp to a second computer hosting a communication service provider. the second computer encrypts the original otp using a private key for a mobile network cell communicating with a mobile device of the user and sends an encrypted otp to the mobile device. upon receiving the encrypted otp from the computing device, the first computer decrypts the encrypted otp, using public keys for one or more cells covering the geofence. upon determining a decrypted otp matches the original otp, the first computer allows the digital service to be provided.
Inventor(s): Shimon Benusovich of Rishon Le Zion (IL) for international business machines corporation, Andrey Finkelshtein of Beer Sheva (IL) for international business machines corporation, Noga Agmon of Givat Shmuel (IL) for international business machines corporation
IPC Code(s): H04L9/40, G06F16/906
CPC Code(s): H04L63/1425
Abstract: mechanisms are provided for detecting fraudulent user flows associated with a website. user flow data, representing an interaction by a user with content of a website, is received and converted to a vector representation that represents a time series transition from one portion of website content to another of the website. the vector representation is input to a trained sequential machine learning computer model which generates a classification of the vector representation. a determination as to whether or not the user flow data represents a fraudulent user flow is made based on the classification. an output is generated that indicates whether or not the user flow is a fraudulent user flow based on the detection.
Inventor(s): NAOTO ITO of Bunkyo-ku (JP) for international business machines corporation, Shuhei Kochi of Tokyo (JP) for international business machines corporation, KENICHI YOKOMIZO of Tokyo (JP) for international business machines corporation, Kohichiroh Nishiue of Chiba (JP) for international business machines corporation
IPC Code(s): H04W24/02, H04L43/0817, H04W4/38, H04W24/10
CPC Code(s): H04W24/02
Abstract: a method, computer system, and a computer program product for network optimization is provided. the present invention may include moving a sensor in a three-dimensional space. the present invention may also include collecting, using the sensor, network performance data in a plurality of locations in the three-dimensional space. the present invention may further include detecting, based on the network performance data, at least one location of the plurality of locations including below-threshold network performance. the present invention may further include predicting at least one root cause for the below-threshold network performance at the at least one location.
Inventor(s): Akira Saito of Ichikawa-shi (JP) for international business machines corporation, Mitsuru Chinen of Yokohama-shi (JP) for international business machines corporation, Takeshi Watanabe of Kawasaki (JP) for international business machines corporation, Taku Sasaki of Machida-shi (JP) for international business machines corporation, Takuya Matsunaga of Ichikawa-shi (JP) for international business machines corporation
IPC Code(s): H04W40/18, H04W40/20
CPC Code(s): H04W40/18
Abstract: a method can include obtaining device data for a set of edge devices. the method can further include obtaining a predicted travel path of a focal entity. the method can further include determining, for a first edge device of the set of edge devices and based on the device data, a first proximity of the first edge device to the predicted travel path. the method can further include selecting the first edge device based, at least in part, on the first proximity. the method can further include transmitting, in response to the selecting the first edge device, a workload to the first edge device. the method can further include receiving, in response to the transmitting the workload, first captured data obtained by the first edge device. the method can further include transmitting the first captured data to an electronic user device.
Inventor(s): Malgorzata Jadwiga Zimon of Warrington (GB) for international business machines corporation, Fausto Martelli of Stockton Heath (GB) for international business machines corporation
IPC Code(s): H05K7/20, F28F13/16, G06F1/20
CPC Code(s): H05K7/20281
Abstract: the present inventive concept provides for a method of microfluid cooling for a non-uniform heatmap. the method includes identifying a plurality of zones of a microelectronic device. a local temperature measurement is obtained for one or more zones of the plurality of zones of the microelectronic device. a voltage is applied to a microfluid in at least a portion of the one or more zones based on the obtained local temperature measurement.
Inventor(s): Michele Aldeghi of Cadro (CH) for international business machines corporation, Rolf Allenspach of Adliswil (CH) for international business machines corporation, Gian R. von Salis of Aeugst am Albis (CH) for international business machines corporation
IPC Code(s): H10N60/80, G06N10/40, H10N60/01, H10N60/10
CPC Code(s): H10N60/80
Abstract: a qubit device comprising: a semiconductor substrate layer; a semiconductor substrate layer; a set of control gates defining one or more lines of two or more quantum dots along the substrate layer, each quantum dot being configured for holding a qubit; and a magnet system providing at the substrate layer a superposition of external and local magnetic fields such that qubit spin resonance frequencies of each pair of adjacent quantum dots in each line are different, the magnet system comprising an external magnetic field source for providing the external magnetic field and comprising a magnet on top of every other quantum dot for providing the local magnetic field.
INTERNATIONAL BUSINESS MACHINES CORPORATION patent applications on December 19th, 2024
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- A61H3/06
- G01S13/60
- G01S13/86
- CPC A61H3/061
- International business machines corporation
- G05B13/02
- CPC G05B13/0265
- G05B23/02
- CPC G05B23/0283
- G05D1/10
- B64U80/00
- CPC G05D1/104
- G06F7/499
- CPC G06F7/49915
- G06F8/41
- CPC G06F8/4432
- G06F8/61
- CPC G06F8/63
- G06F8/65
- CPC G06F8/65
- G06F9/451
- G06F3/04845
- CPC G06F9/453
- G06F9/50
- CPC G06F9/5033
- G06F9/445
- G06N7/01
- CPC G06F9/505
- G06F16/23
- G06F9/54
- G06F11/34
- CPC G06F9/546
- G06F11/07
- CPC G06F11/076
- G06F12/0815
- CPC G06F12/0815
- G06F12/1027
- G06F12/02
- CPC G06F12/1027
- G06F16/22
- G06F16/27
- CPC G06F16/2219
- G06F16/2455
- CPC G06F16/2282
- G06F16/28
- G06F16/215
- CPC G06F16/285
- G06F16/332
- CPC G06F16/3329
- G06F16/33
- CPC G06F16/3335
- G06F16/908
- CPC G06F16/908
- G06F16/9535
- CPC G06F16/9535
- G06F17/16
- CPC G06F17/16
- G06F17/40
- G06F17/15
- CPC G06F17/40
- G06F21/46
- CPC G06F21/46
- G06F30/33
- CPC G06F30/33
- G06F30/39
- CPC G06F30/39
- G06F40/151
- G06F40/166
- G06F40/20
- CPC G06F40/151
- G06F40/58
- G06F40/205
- G06F40/242
- G06F40/51
- G06V30/10
- CPC G06F40/58
- G06N3/0464
- CPC G06N3/0464
- G06N3/08
- G06N3/045
- CPC G06N3/08
- G06N3/084
- CPC G06N3/084
- G06N5/04
- CPC G06N5/04
- G06N10/40
- H01P1/38
- CPC G06N10/40
- G06N20/00
- CPC G06N20/00
- G06Q10/04
- CPC G06Q10/04
- G06Q10/10
- G06Q50/00
- CPC G06Q10/103
- G10L15/18
- G10L15/22
- G06Q30/0601
- G06T19/00
- CPC G06Q30/0631
- G06T7/00
- G06T7/73
- G06V10/764
- G06V10/77
- G06V10/774
- G06V30/19
- G06V30/413
- CPC G06T7/0002
- G06V10/74
- CPC G06T19/006
- CPC G06V10/774
- G06V20/52
- G06T7/80
- G06V10/82
- G06V20/70
- G10L21/0208
- CPC G06V20/52
- G07C5/00
- G08G1/00
- CPC G07C5/008
- G09B7/02
- G06N5/02
- CPC G09B7/02
- G09B21/00
- G06F3/01
- G06F3/16
- G10L15/26
- CPC G09B21/009
- CPC G10L15/1815
- G11C13/00
- G11C11/54
- CPC G11C13/0069
- H01L21/28
- H01L29/06
- H01L29/423
- H01L29/49
- H01L29/66
- H01L29/775
- CPC H01L21/28123
- H01L29/417
- H01L21/762
- H01L21/84
- H01L27/12
- CPC H01L21/76224
- H01L21/8234
- H01L21/768
- H01L23/528
- H01L27/088
- H01L29/08
- CPC H01L21/823475
- H01L23/48
- H01L29/786
- CPC H01L23/481
- H01L21/8238
- H01L27/092
- H01L23/522
- CPC H01L23/5223
- H01L23/532
- CPC H01L23/5226
- CPC H01L23/528
- CPC H01L23/5283
- H01L29/40
- CPC H01L23/5286
- H01L23/498
- H01L23/535
- H01L23/00
- H01L25/18
- H10N60/81
- CPC H01L24/17
- H01L27/02
- H10B10/00
- CPC H01L27/0207
- CPC H01L27/0922
- G11C16/34
- CPC H01L29/0607
- CPC H01L29/0847
- H04L9/32
- CPC H04L9/3236
- H04L41/0668
- G16Y10/75
- G16Y30/00
- H04L67/568
- CPC H04L41/0668
- H04L47/122
- H04L43/0817
- H04L47/2425
- CPC H04L47/122
- H04L9/40
- H04L51/48
- CPC H04L63/0442
- H04W4/021
- CPC H04L63/0838
- G06F16/906
- CPC H04L63/1425
- H04W24/02
- H04W4/38
- H04W24/10
- CPC H04W24/02
- H04W40/18
- H04W40/20
- CPC H04W40/18
- H05K7/20
- F28F13/16
- G06F1/20
- CPC H05K7/20281
- H10N60/80
- H10N60/01
- H10N60/10
- CPC H10N60/80
