VERTICAL CHANNEL TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Organization Name

huawei technologies co., ltd.

Inventor(s)

Kailiang Huang of Shenzhen CN

Weiliang Jing of Shanghai CN

Zhaogui Wang of Shanghai CN

Junxiao Feng of Shenzhen CN

Zhengbo Wang of Beijing CN

VERTICAL CHANNEL TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

This abstract first appeared for US patent application 20250008746 titled 'VERTICAL CHANNEL TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Original Abstract Submitted

embodiments of this disclosure relate to a vertical channel transistor structure. an example vertical channel transistor structure includes a stacked structure. the stacked structure includes a first metal layer, a first contact layer, an insulation dielectric layer, a second contact layer, a second metal layer, and a groove. the first contact layer is located between the first metal layer and the insulation dielectric layer, and the second contact layer is located between the second metal layer and the insulation dielectric layer. the groove penetrates the second metal layer, the second contact layer, the insulation dielectric layer, and the second contact layer. the groove is at least partially recessed into the first metal layer. the groove includes a semiconductor channel layer, a gate oxygen dielectric layer, and a gate.