Huawei technologies co., ltd. (20240259022). LOGIC GATE CIRCUIT, LATCH, AND FLIP-FLOP
LOGIC GATE CIRCUIT, LATCH, AND FLIP-FLOP
Organization Name
Inventor(s)
JEFFREY JUNHAO Xu of Shenzhen CN
LOGIC GATE CIRCUIT, LATCH, AND FLIP-FLOP
This abstract first appeared for US patent application 20240259022 titled 'LOGIC GATE CIRCUIT, LATCH, AND FLIP-FLOP
Original Abstract Submitted
a logic gate circuit includes a pull-up network, a pull-down network, a signal output end, at least one signal input end, a first voltage end, and a second voltage end. the pull-up network includes a first gate and a second gate. a first electrode of the first nfet and the first gate are connected to the first voltage end. a second electrode of the first nfet and the second gate are connected to the signal output end. the pull-down network includes a second nfet. the pull-down network is connected to the signal output end, the at least one signal input end, and the second voltage end. the pull-down network is configured to: control the second nfet based on a voltage of the at least one signal input end, and pull down a voltage of the signal output end by using a voltage of the second voltage end.