Fujitsu Limited patent applications on February 20th, 2025
Patent Applications by Fujitsu Limited on February 20th, 2025
Fujitsu Limited: 17 patent applications
Fujitsu Limited has applied for patents in the areas of G06F9/50 (2), G06F17/11 (2), G06F9/30 (1), H04L5/00 (1), H10N60/01 (1) G06F17/11 (2), G06F9/30036 (1), G06F9/5027 (1), G06F18/211 (1), G06N3/096 (1)
With keywords such as: value, pipeline, surface, process, state, based, layer, parameter, transmission, and electrode in patent application abstracts.
Patent Applications by Fujitsu Limited
Inventor(s): Yuji KATAOKA of Yokohama (JP) for fujitsu limited
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30036
Abstract: a non-transitory computer-readable recording medium storing an arithmetic program for causing a computer to execute processing including: generating a first vector by extracting each of elements of a matrix of a plurality of pieces of analysis data represented as two-dimensional data; creating a first normalized vector by normalizing each of the elements of the first vector; generating a second vector by extracting each of elements of a matrix of characteristic data that corresponds to the plurality of pieces of analysis data; creating a second normalized vector by normalizing each of the elements of the second vector; and specifying a correspondence relationship between the element included in the first vector and the element included in the second vector according to similarity between the first normalized vector and the second normalized vector.
Inventor(s): Akira URA of Yokohama (JP) for fujitsu limited
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5027
Abstract: a non-transitory computer-readable recording medium stores a pipeline set generation program for causing a computer to execute a process including: acquiring a first pipeline set of which each of pipelines includes a machine learning model, based on a plurality of tasks; generating a second pipeline set by adding specified components that correspond to each class of variables included in data of the plurality of tasks to each of the pipelines included in the first pipeline set; and acquiring evaluation values for each of the pipelines included in the second pipeline set, by executing the second pipeline set on the plurality of tasks; and generating a third pipeline set by selecting a plurality of the pipelines from the second pipeline set, based on the evaluation values.
Inventor(s): Masayoshi HASHIMA of Kawasaki (JP) for fujitsu limited, Nobuyuki HARA of Meguro (JP) for fujitsu limited
IPC Code(s): G06F17/11
CPC Code(s): G06F17/11
Abstract: a program of performing cut problem calculation on a target including nodes and edges set with weight values, the cut problem calculation including calculating a total weight value of edges cut when the nodes is divided into two groups, the program causing a computer to execute: performing the cut problem calculation without designating the number of divisions and specifying a calculation result of which the total value of the weight values satisfies a first condition, from among calculation results; specifying a calculation result satisfying a second condition; performing the cut problem calculation in which the number of divisions is designated and specifying a calculation result of which the total value of the weight values satisfying a third condition; and calculating a normalized value obtained by normalizing the total value of the weight values and acquiring the number of divisions satisfying a fourth condition from among the normalized values.
Inventor(s): Yutaka TAMIYA of Yokohama (JP) for fujitsu limited
IPC Code(s): G06F17/11, G06F9/50
CPC Code(s): G06F17/11
Abstract: a non-transitory computer-readable recording medium stores a program for causing a computer to execute a process for processing information which includes: obtaining a first nonlinear function to be mapped, calculation accuracy, and an implementation constraint, which are required to implement a nonlinear function in an accelerator; mapping the first nonlinear function to the accelerator to satisfy the calculation accuracy using a predetermined mapping method; determining whether or not a result of the mapping to the accelerator satisfies the implementation constraint; and when the implementation constraint is not satisfied, repeating the mapping and the determining using a mapping method different from the predetermined mapping method.
Inventor(s): Kazuhiro MATSUMOTO of Kawasaki (JP) for fujitsu limited
IPC Code(s): G06F18/211
CPC Code(s): G06F18/211
Abstract: a recording medium stores a program for causing a computer to execute processing including: generating rules that indicates an answer pattern to questions included in questions, based on questionnaire data that indicates answers of respondents to each of the questions in a conducted questionnaire survey; specifying a respondent who has provided a correct answer that is same as an answer pattern to a question indicated in a rule, for each of the rules, based on the questionnaire data; and determining a first rule selection pattern, based on the number of questions included in selected rules, from among rule selection patterns that satisfy a first constraint condition that each of the respondents is specified as the respondent who has provided the correct answer by any one of the single or the selected rules, among rule selection patterns generated by selecting the single or the rules from among the rules.
20250061341. GRAPH REPRESENTATIONS_simplified_abstract_(fujitsu limited)
Inventor(s): Arnab Kumar MONDAL of Bangalore (IN) for fujitsu limited, Jay Nandy of Bangalore (IN) for fujitsu limited
IPC Code(s): G06N3/096, G06N3/045
CPC Code(s): G06N3/096
Abstract: a computer-implemented method comprising performing a training process, the training process comprising: using a student graph neural network, gnn, to extract a pair of first representations from a pair of training graphs, respectively; computing a disagreement between the first representations; using at least one teacher gnn to extract a pair of second representations from the pair of training graphs, respectively; computing a perceptual distance between the second representations; comparing the disagreement between the first representations with a target disagreement which is based at least in part on the perceptual distance between the second representations; and adjusting at least one weight of the student gnn based on the comparison.
Inventor(s): Masahiko SUGIMURA of Kawasaki (JP) for fujitsu limited
IPC Code(s): G06N5/01
CPC Code(s): G06N5/01
Abstract: a non-transitory computer-readable recording medium storing a program for causing a computer to execute processing including: calculating, when a value of any one state variable among a plurality of state variables is updated in a solution search based on an evaluation function that includes the plurality of state variables, a first index value related to a change amount of a value of the evaluation function in a case where a value of a first state variable among the plurality of state variables is updated from values of the plurality of state variables before the update; and determining, based on the first index value, a length of a period of time during which update of the value of the first state variable is suppressed after the value of the first state variable is updated.
Inventor(s): Naoki IIJIMA of Kawasaki (JP) for fujitsu limited, Satoshi IMAMURA of Kawasaki (JP) for fujitsu limited
IPC Code(s): G06N10/60, G16C20/20
CPC Code(s): G06N10/60
Abstract: a recording medium stores a program for executing processing of: obtaining a first value of each first parameter calculated first by the vqe that calculates values of parameter of a quantum circuit and a second value of each first parameters calculated last by the vqe when an active space of a target molecule is reduced; obtaining a third value of each second parameter calculated first by the vqe such that the parameters are calculated once, when the active space of the target molecule is not reduced; specifying one first parameter corresponding to the first value closest to the third value of the second parameter to associate the specified first parameter with the second parameter; and when the active space of the target molecule is not reduced, setting an initial value of each second parameter to the second value of one first parameter specified to be associated with each second parameter.
Inventor(s): Akira URA of Yokohama (JP) for fujitsu limited
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: a non-transitory computer-readable recording medium stores a pipeline set generation program causing a computer to execute a process including: acquiring, based on a plurality of tasks, a pipeline set in which each pipeline includes a machine learning model; generating a second pipeline by executing a simplification process which includes at least one of a process of deleting a component included in the pipeline and a process of changing a hyper parameter of the component included in the pipeline to a default value on a first pipeline of the pipeline set; acquiring an evaluation value of the second pipeline by executing the second pipeline for the plurality of tasks; and adding the second pipeline to the pipeline set based on the evaluation value.
20250061699. IMAGE ENCODING_simplified_abstract_(fujitsu limited)
Inventor(s): Naga Sri Krishna Chaitanya DEVAGUPTAPU of Bangalore (IN) for fujitsu limited, Sumukh K AITHAL of Bangalore (IN) for fujitsu limited
IPC Code(s): G06V10/82, G06V10/77
CPC Code(s): G06V10/82
Abstract: a computer-implemented method comprising performing a training process, the training process comprising: using first and second image encoder networks, generating first and second sets of embeddings based on a pair of first and second input images, respectively; generating first and second nearest neighbor graphs, nngs, based on the first and second sets of embeddings, respectively; using at least one graph neural network, gnn, extracting first and second representations from the first and second nngs, respectively; and adjusting at least one network weight of the first image encoder network based on a difference between the first and second representations.
Inventor(s): Ryu SHINZAKI of Ota (JP) for fujitsu limited, Motohiko ETO of Kawasaki (JP) for fujitsu limited, Kyosuke SONE of Kawasaki (JP) for fujitsu limited, Setsuo YOSHIDA of Inagi (JP) for fujitsu limited, Kazuyuki TAJIMA of Yokosuka (JP) for fujitsu limited, Tomoaki TAKEYAMA of Yokohama (JP) for fujitsu limited, Shoichiro ODA of Fuchu (JP) for fujitsu limited
IPC Code(s): H04B10/61, H04B10/079
CPC Code(s): H04B10/6165
Abstract: a transmission line parameter estimation apparatus includes: a storage unit configured to stores in advance a non-linear phase rotation amount distribution obtained by using time waveform data acquired from a receiver, of a first transmission line, and a non-linear phase rotation amount of a second transmission line different from the first transmission line; and a controller configured to refer to data in the storage unit, and obtains a non-linear constant of each span of the second transmission line based on a distribution of the non-linear phase rotation amount.
Inventor(s): Jian ZHANG of Beijing (CN) for fujitsu limited, Gang SUN of Beijing (CN) for fujitsu limited, Di ZHAO of Beijing (CN) for fujitsu limited
IPC Code(s): H04L5/00, H04L27/26
CPC Code(s): H04L5/0048
Abstract: a signal transmission apparatus includes: a receiver configured to receive tci (transmission configuration indicator) state indication information, the tci state indication information indicating at least one tci state; processor circuitry configured to determine an srs (sounding reference signal) resource set associated with an indicated tci state in configured multiple srs resource sets; and a transmitter configured to: perform uplink transmission by using a parameter associated with the srs resource set associated with the tci state and/or a parameter associated with the tci state, and perform uplink transmission for dynamic grant pusch (physical uplink shared channel) scheduled by dci (downlink control information) format 0_0 or type 2 configured grant pusch activated by dci format 0_0, wherein the dynamic grant pusch or the type 2 configured grant pusch is associated with a first srs resource set and/or a first tci state associated with the first srs resource set.
Inventor(s): Takeshi Miyamae of Kawasaki (JP) for fujitsu limited
IPC Code(s): H04L9/32
CPC Code(s): H04L9/3218
Abstract: a non-transitory computer-readable recording medium stores a proof generation program that causes a computer to execute a process including: generating, for each process included in a supply chain, zero-knowledge proof that indicates validity of a cumulative value obtained by accumulating a value of each process from a most upstream process to the process and information regarding the cumulative value; and causing a blockchain to record the zero-knowledge proof and the information regarding the cumulative value.
Inventor(s): Tetsuya YANO of Yokohama (JP) for fujitsu limited, YOSHIHIRO KAWASAKI of Kawasaki (JP) for fujitsu limited
IPC Code(s): H04W24/02
CPC Code(s): H04W24/02
Abstract: a base station device includes a plurality of wireless stations, the wireless stations each includes: a receiver that receives signals transmitted from a plurality of wireless terminal devices that transmit transmission data in a coordinated manner, and a controller that selects a reference wireless station from among the wireless stations, determines a phase of the transmission data for each of the wireless terminal devices at the selected reference wireless station, and notifies the wireless terminal devices of the determined phase.
Inventor(s): Ryota KOSAKA of Kawasaki (JP) for fujitsu limited, Takashi SEYAMA of Kawasaki (JP) for fujitsu limited
IPC Code(s): H04W52/24, H04W52/10
CPC Code(s): H04W52/243
Abstract: a control device in a communication system that includes base stations each to constitute a cell, and a terminal to perform wireless communication with the base station when the terminal is positioned in the cell, the control device controlling the base stations, includes a memory, and processor circuitry coupled to the memory and configured to acquire, from the base station, an interference value measured when a signal is received from the terminal by the base station, estimate, when a transmission power of a first terminal that communicates with a first base station is controlled in accordance with a value of a path loss for the first base station, a maximum-given-interference-amount, among given-interferences of the first terminal for an other base station other than the first base station, and acquire a corrected value for correcting the transmission power of the first terminal by using the maximum-given-interference-amount.
Inventor(s): Kenji HOMMA of Atsugi (JP) for fujitsu limited, Atsushi YAMADA of Hiratsuka (JP) for fujitsu limited
IPC Code(s): H01L29/778, H01L29/20, H01L29/66
CPC Code(s): H01L29/7786
Abstract: a semiconductor device includes: a channel layer that includes a first nitride semiconductor; a barrier layer provided on a first surface side of the channel layer and includes a second nitride semiconductor; a source electrode and a drain electrode provided on a second surface side opposite to the channel layer side, of the barrier layer; a gate electrode provided between the source electrode and the drain electrode, on the second surface side of the barrier layer; and a polarization layer that is provided between the gate electrode and the drain electrode, from among between the gate electrode and the source electrode and between the gate electrode and the drain electrode on the second surface side of the barrier layer, includes a third nitride semiconductor that contains al, and has an al composition that decreases from the barrier layer side toward a third surface side opposite to the barrier layer side.
Inventor(s): Akihiko SEKINE of Arakawa (JP) for fujitsu limited, Manabu OHTOMO of Kawasaki (JP) for fujitsu limited
IPC Code(s): H10N60/01, H10N60/85
CPC Code(s): H10N60/0884
Abstract: a quantum device includes: a higher-order topological insulator layer; and a superconductor layer. the higher-order topological insulator layer has a first surface and a second surface parallel to each other, a third surface that intersects with the second surface and is located closer to a first surface side than the second surface, and a fourth surface that intersects with the third surface and is parallel to the first surface and the second surface, and the superconductor layer is formed over an intersection line of a plane that includes the third surface and the first surface.
- Fujitsu Limited
- G06F9/30
- CPC G06F9/30036
- Fujitsu limited
- G06F9/50
- CPC G06F9/5027
- G06F17/11
- CPC G06F17/11
- G06F18/211
- CPC G06F18/211
- G06N3/096
- G06N3/045
- CPC G06N3/096
- G06N5/01
- CPC G06N5/01
- G06N10/60
- G16C20/20
- CPC G06N10/60
- G06N20/00
- CPC G06N20/00
- G06V10/82
- G06V10/77
- CPC G06V10/82
- H04B10/61
- H04B10/079
- CPC H04B10/6165
- H04L5/00
- H04L27/26
- CPC H04L5/0048
- H04L9/32
- CPC H04L9/3218
- H04W24/02
- CPC H04W24/02
- H04W52/24
- H04W52/10
- CPC H04W52/243
- H01L29/778
- H01L29/20
- H01L29/66
- CPC H01L29/7786
- H10N60/01
- H10N60/85
- CPC H10N60/0884
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