Dell Products L.P. patent applications on May 8th, 2025
Patent Applications by Dell Products L.P. on May 8th, 2025
Dell Products L.P.: 24 patent applications
Dell Products L.P. has applied for patents in the areas of G06F9/50 (4), G06N10/40 (3), H05K1/11 (2), G06F3/06 (2), H05K3/34 (2) G06N10/40 (2), G06F1/184 (1), G06F12/0848 (1), H05K1/111 (1), H05K1/0284 (1)
With keywords such as: node, circuit, quantum, storage, data, cache, information, processing, computing, and resources in patent application abstracts.
Patent Applications by Dell Products L.P.
Inventor(s): COREY DEAN HARTMAN of Hutto TX US for dell products l.p., SANJIV SINHA of Austin TX US for dell products l.p.
IPC Code(s): G06F1/18
CPC Code(s): G06F1/184
Abstract: methods and systems for managing power distribution and/or mechanical load in data processing systems is provided. the power distribution may be managed using multifunction power buses that may relieve a motherboard of a data processing system from distributing power. the mechanical load may be managed using an adapter plate that may relieve the motherboard of the data processing system from providing for attachment of devices based on the location of the mechanical mounting hardware on the devices. by doing so, motherboards may be standardized and customized for use with various devices.
Inventor(s): Sanjib Mallick of Bangalore IN for dell products l.p., Vinay G. Rao of Bangalore IN for dell products l.p., Krishna Deepak Nuthakki of Bangalore IN for dell products l.p., Arieh Don of Newton MA US for dell products l.p.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0604
Abstract: an apparatus in an illustrative embodiment comprises at least one processing device comprising a processor coupled to a memory. the at least one processing device is configured to receive in a storage system from at least one host device at least first and second different input-output timeout values for respective first and second different logical storage devices of the storage system, to store the received input-output timeout values in association with respective identifiers of the first and second logical storage devices in at least one data structure of the storage system, and to control processing of input-output operations, received in the storage system from the at least one host device and targeting respective ones of the first and second logical storage devices, based at least in part on the corresponding input-output timeout values stored in the at least one data structure of the storage system.
Inventor(s): Kuolin Hua of Natick MA US for dell products l.p., Kunxiu Gao of Boxborough MA US for dell products l.p., Malak Alshawabkeh of Franklin MA US for dell products l.p.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0616
Abstract: a container system facilitates selective migrations of data from high-wear inducing data devices to spare data devices to promote ssd wear levelling. storage capacity is configured into same-size cells with each container having the same number of cells as raid width w. the cells are distributed over w ssds. the containers are subdivided into equal-size data devices, each distributed over the same set of w ssds as its associated container. candidate migration source-target pairs are selected using heuristics guided by a prediction model that correlates disk wear rate with total writes of existing workloads. wear rate predictions are computed using a weighted sum of write rates of all data devices on a disk. wear rate predictions for candidate migration pairs are computed inclusive of additional wear caused by data migration to select a migration plan.
20250147774. CONTEXT AWARE SCALING IN A DISTRIBUTED SYSTEM_simplified_abstract_(dell products l.p.)
Inventor(s): Parmeshwr Prasad of Bangalore IN for dell products l.p., Ravishankar N of Bangalore IN for dell products l.p., Anubhav Singh of Pune IN for dell products l.p.
IPC Code(s): G06F9/445
CPC Code(s): G06F9/44505
Abstract: a distributed processing system includes a cloud-based network and a back-end system. the cloud-based network has an orchestrator and a plurality of application pods. each application pod includes an application and an exporter configured to provide telemetry information for the associated application. the back-end system has an application analysis module that receives the telemetry information from the application pods, determines an interdependency between the applications, determines a scaling between the applications, and directs the orchestrator to launch the applications based on the scaling.
20250147793. NUMA NODE VIRTUAL MACHINE PROVISIONING SYSTEM_simplified_abstract_(dell products l.p.)
Inventor(s): Jose Miguel Grande, JR. of Round Rock TX US for dell products l.p., Yi-Shu Hung of Taipei City TW for dell products l.p.
IPC Code(s): G06F9/455, G06F9/50, G06F13/42
CPC Code(s): G06F9/45558
Abstract: a non-uniform memory access (numa) node virtual machine provisioning system includes a connection system and a physical numa node coupled to a numa node virtual machine provisioning subsystem that modifies numa node information in at least one database to create a first virtual numa node that is provided by a first subset of numa node resources in the physical numa node, modifies connection system information in the at least one database to dedicate a first subset of connection system resources in the connection system to the first virtual numa node, and deploys a first virtual machine on the first virtual numa node such that the first virtual machine performs operations using the first subset of numa node resources that provide the first virtual numa node, and using the first subset of connection system resources dedicated to the first virtual numa node.
Inventor(s): Victor Fong of Medford MA US for dell products l.p., Brendan Burns Healy of Haddonfield NJ US for dell products l.p., Miguel Paredes Quiñones of Campinas BR for dell products l.p.
IPC Code(s): G06F9/50, G06N10/40, G06N10/60
CPC Code(s): G06F9/5027
Abstract: one example method includes receiving a user job that includes a quantum computing workload, evaluating the quantum computing workload, based on the evaluating, solving an orchestration optimization problem by identifying a computing resource for execution of the quantum computing workload, and the computing resource is selected from a defined group of computing resources of a computing infrastructure, and orchestrating the quantum computing workload to the computing resource for execution.
Inventor(s): Farzad Khosrowpour of Pflugerville TX US for dell products l.p., Mitchell Markow of Hutto TX US for dell products l.p.
IPC Code(s): G06F9/50
CPC Code(s): G06F9/505
Abstract: an information handling system includes resource detection circuitry that collects data associated with resources being utilized in the information handling system. the system determines resources for execution of an inference model, and receives the data associated with the resources from the resource detection circuitry. based on the resources for the execution of the inference model, the system determines one performance of an application when the inference model is executed in the information handling system. the system determines another performance level of the application when the inference model is not executed in the information handling system. based on the two performance levels, the system determines whether the application has a performance gain by the inference model not being executed in the information handling system. in response to the performance gain, the system migrates the inference model to an edge server for execution.
Inventor(s): Phuong N. Hoang of San Jose CA US for dell products l.p., Sukarna Grandhi of Fremont CA US for dell products l.p., Thomas Watson of Richardson TX US for dell products l.p.
IPC Code(s): G06F11/14, G06F9/50
CPC Code(s): G06F11/1446
Abstract: embodiments of a method for providing cluster-wide, application consistent operations in a distributed network by creating a single volume snapshot object on a server for all of volumes of a distributed application. a snapshot controller creates volume snapshot content for each volume, and an external snapshot process, upon creation of the volume snapshot content, creates a snapshot of each volume on a backend storage device, wherein all snapshots for each volume are created at the same time to ensure consistency across all volumes being snapshotted at a certain moment.
20250147853. METADATA SIMULATION_simplified_abstract_(dell products l.p.)
Inventor(s): Kanuri Venkata Satyanarayana Swami of Bangalore IN for dell products l.p., Steve Lathrop of Milford MA US for dell products l.p., Anoop Raghunathan of Ashland MA US for dell products l.p.
IPC Code(s): G06F11/22
CPC Code(s): G06F11/2273
Abstract: one or more aspects of the present disclosure relate to simulating an input/output (io) workload. in embodiments, information corresponding to one or more characteristics of an input/output (io) workload is received. in addition, metadata corresponding to the io workload is generated using the information. further, testing of a storage array can be enabled using the metadata.
Inventor(s): Dustin H. Zentz of Shrewsbury MA US for dell products l.p., Dan Aharoni of Brookline MA US for dell products l.p., Igal Moshkovich of Even Yehuda IL for dell products l.p.
IPC Code(s): G06F11/30, G06F11/34
CPC Code(s): G06F11/3034
Abstract: a method in an illustrative embodiment comprises collecting performance measurement data for processing of input-output operations sent by a host to a storage system for a first period of time prior to a configuration change and a second period of time subsequent to the configuration change, processing performance measurement data for the first period of time to determine a first point in a plane defined by a first performance metric and a second performance metric, processing performance measurement data for the second period of time to determine a second point in the plane defined by the first and second performance metrics, determining one or more characteristics of a positioning of the second point relative to the first point, and controlling execution of at least one automated action relating to at least one of the host and the storage system based at least in part on the one or more characteristics.
20250147882. BOARD LEVEL DYNAMIC CACHE LAYOUT DISTRIBUTION_simplified_abstract_(dell products l.p.)
Inventor(s): John Creed of Innishannon IE for dell products l.p.
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0802
Abstract: one or more aspects of the present disclosure relate to cache layout optimization. in embodiments, an input/output (io) workload is received by a storage array. additionally, a system-level cache layout distribution model is established based on one or more characteristics of the io workload. further, cache slot allocations are dynamically adjusted for each cache segment of global memory for each board based on the system-level cache layout distribution model and the one or more characteristics of the io workload.
Inventor(s): Vladimir Shveidel of Pardes-Hana IL for dell products l.p., Vamsi K. Vankamamidi of Hopkinton MA US for dell products l.p.
IPC Code(s): G06F12/0831, G06F12/0882, G06F12/0891
CPC Code(s): G06F12/0835
Abstract: techniques for processing a read i/o operation that reads first content stored at a target logical address can include: determining, using the target logical address as a first key to index into a first cache, whether the first cache includes a first cache entry caching first metadata used to access a first physical storage location including the first content stored at the target logical address; responsive to determining the first cache includes the first cache entry, determining, using the first metadata as a second key to index into a second cache, whether the second cache includes a second cache entry caching the first content stored at the target logical address; and responsive to determining the second cache includes the second entry, returning the first content from the second entry of the second cache in response to the read i/o operation.
20250147891. CACHE LAYOUT OPTIMIZATION_simplified_abstract_(dell products l.p.)
Inventor(s): Malak Alshawabkeh of Franklin MA US for dell products l.p., Kaustubh Sahasrabudhe of Westborough MA US for dell products l.p., Ramesh Doddaiah of Westborough MA US for dell products l.p.
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0848
Abstract: one or more aspects of the present disclosure relate to cache layout optimization. in embodiments, an input/output (io) workload is received by a storage array. further, cache slot allocations are dynamically adjusted for each cache segment of global memory based on one or more characteristics of the io workload.
Inventor(s): Ramesh Doddaiah of Westborough MA US for dell products l.p., Owen Martin of Hopedale MA US for dell products l.p.
IPC Code(s): G06F13/20, G06F15/82
CPC Code(s): G06F13/20
Abstract: a storage system is configured with pools of processor cores. each pool corresponds uniquely to one of the supported service levels of the storage system. processor cores within each pool run at a clock speed that is defined for the service level corresponding to the respective pool. incoming ios are enqueued for processing by cores of the pool corresponding to the service level of the storage group containing the storage object that is the target of the io. forecast io demand and corresponding data access latency are computed for each service level. if the forecast latency of a service level includes values outside a compliance range, then cores are promoted to, or demoted from, the corresponding pool so that forecast latency stays within the compliance range, thereby reducing power consumption while promoting service level compliance.
Inventor(s): Adolfo S. Montero of Pflugerville TX US for dell products l.p.
IPC Code(s): G06F13/42, G06F1/20, G06F13/40
CPC Code(s): G06F13/4221
Abstract: systems and methods for loading firmware onto an external embedded controller (ec) of a heterogenous computing platform. in an illustrative, non-limiting embodiment, an information handling system (ihs) may include: a heterogeneous computing platform having a reduced instruction set computer (risc) processor and a peripheral component interconnect express (pcie) controller coupled thereto, and an ec external to the heterogeneous computing platform and coupled to the pcie controller, wherein the ec is configured to retrieve at least one of: firmware instructions, a configuration setting, or a table, from a pcie device coupled to the pcie controller.
Inventor(s): Jonathan Mendes De Almeida of Brasília BR for dell products l.p., Renam Castro Da Silva of São José dos Campos BR for dell products l.p., Victor da Cruz Ferreira of Rio de Janeiro BR for dell products l.p.
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: techniques are disclosed for sparse layer-wise training of neural networks. an example system includes at least one processing device including a processor coupled to a memory. the at least one processing device can be configured to implement the following steps: obtaining class predictions while saving activations for only a number ‘k’ layers of a neural network, using the class predictions to calculate a layer shallowness measure for the neural network, using the layer shallowness measure to determine a number ‘u’ of layers to update in the neural network, and partially updating the neural network by training only the number ‘u’ layers of the neural network.
Inventor(s): Brendan Burns Healy of Haddonfield NJ US for dell products l.p., Benjamin E. Santaus of Somerville MA US for dell products l.p., Rômulo Teixeira de Abreu Pinho of Niterói BR for dell products l.p.
IPC Code(s): G06N10/20, G06F17/16
CPC Code(s): G06N10/20
Abstract: one example method includes obtaining, for a quantum gate of a quantum circuit, an estimate of a distribution of values expected to result from a matrix multiplication relating to the quantum gate, applying a binning process to the distribution to generate a bin table, quantizing an fp value of the matrix multiplication by mapping the bin table to a bin index that corresponds to the fp value, storing the bin index, and performing the matrix multiplication using the bin index.
Inventor(s): Victor Fong of Medford MA US for dell products l.p., Brendan Burns Healy of Haddonfield NJ US for dell products l.p., Benjamin E. Santaus of Somerville MA US for dell products l.p., Miguel Paredes Quiñones of Campinas BR for dell products l.p., Rômulo Teixeira de Abreu Pinho of Niterói BR for dell products l.p.
IPC Code(s): G06N10/40, G06N10/20
CPC Code(s): G06N10/40
Abstract: dynamic orchestration of quantum circuit execution. a runtime prediction is performed on a quantum circuit to determine or estimate an amount of resources and execution time that are needed to execute the quantum circuit. the runtime prediction may also estimate the resources, time, and other factors associated with cutting the quantum circuit. when cutting the circuit is beneficial, the quantum subcircuits generated by cutting the quantum circuit are subject to runtime prediction. this information generated by the runtime prediction, along with telemetry data from computing and quantum resources and service level objectives, is used to generate an execution plan for performing or executing the quantum circuit or the quantum subcircuits when the quantum circuit is cut.
Inventor(s): Victor Fong of Medford MA US for dell products l.p., Brendan Burns Healy of Haddonfield NJ US for dell products l.p., Benjamin E. Santaus of Somerville MA US for dell products l.p., Miguel Paredes Quiñones of Campinas BR for dell products l.p., Rômulo Teixeira de Abreu Pinho of Niterói BR for dell products l.p.
IPC Code(s): G06N10/40
CPC Code(s): G06N10/40
Abstract: cutting quantum circuits is disclosed. probability distributions for quantum circuit parameters are generated from historical quantum circuit data. when cutting the quantum circuit, the probability distributions are sampled to obtain a set of initial circuit parameters that can function as constraints in the cutting operation.
Inventor(s): Jonathan Mendes De Almeida of Brasília BR for dell products l.p., Eduarda Tatiane Caetano Chagas of Belo Horizonte BR for dell products l.p., Paulo Abelha Ferreira of Rio de Janeiro BR for dell products l.p.
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: techniques are disclosed for explainable federated learning. an example method includes receiving, at a central node, relative importances for a plurality of features input into a machine learning (ml) model usable at an edge node, thereby defining a plurality of feature importances, the central node being configured to communicate with the edge nodes; using, at the central node, an ml algorithm to classify the edge nodes into a number ‘k’ of node groups based on the feature importances; and for each node group among the ‘k’ node groups: generating, at the central node, an ml shared model using the feature importances associated with a selected subset of nodes in the node group; and deploying, at the central node, the shared model to each edge node in the node group.
Inventor(s): James L. PETIVAN of Austin TX US for dell products l.p., Earl BOONE of Round Rock TX US for dell products l.p., Wallace H. ABLES of Georgetown TX US for dell products l.p., Steven R. ETHRIDGE of Austin TX US for dell products l.p.
IPC Code(s): H01L23/00, H01L21/48, H01L23/49, H01L23/498
CPC Code(s): H01L24/13
Abstract: an information handling resource may include a circuit board comprising an electrically-conductive pad, a circuit package comprising an electrically-conductive pin, and reflowed solder electrically coupling the electrically-conductive pad to the electrically-conductive pin, the reflowed solder having embedded therein at least one bead configured to provide mechanical standoff between the pad and the pin.
Inventor(s): Earl BOONE of Round Rock TX US for dell products l.p., James L. PETIVAN of Austin TX US for dell products l.p., Wallace H. ABLES of Georgetown TX US for dell products l.p., Steven R. ETHRIDGE of Austin TX US for dell products l.p.
IPC Code(s): H05K1/02, H05K1/11, H05K1/18, H05K3/00, H05K3/04, H05K3/34
CPC Code(s): H05K1/0284
Abstract: an information handling resource may include a circuit board comprising an electrically-conductive pad and a dimple formed on the circuit board, the dimple having a depression surrounded by a raised perimeter raised above a surface of the circuit board.
Inventor(s): Steven R. ETHRIDGE of Austin TX US for dell products l.p., Earl BOONE of Round Rock TX US for dell products l.p., James L. PETIVAN of Austin TX US for dell products l.p., Wallace H. ABLES of Georgetown TX US for dell products l.p.
IPC Code(s): H05K1/11, H05K1/18, H05K3/34
CPC Code(s): H05K1/111
Abstract: an information handling resource may include a circuit board comprising an electrically-conductive pad and a plated standoff plated onto a surface of the electrically-conductive pad.
Inventor(s): Steven R. ETHRIDGE of Austin TX US for dell products l.p., Sandor T. FARKAS of Round Rock TX US for dell products l.p., Bhyrav M. MUTNURY of Austin TX US for dell products l.p.
IPC Code(s): H05K3/46, H05K1/02, H05K3/24
CPC Code(s): H05K3/4655
Abstract: a method for forming a circuit board may include, in a conductive layer of the circuit board, applying a layer of metal foil to a first insulating layer of the circuit board, selectively plating the layer of metal with additional metal, removing portions of the layer of metal foil such that the selectively plating and removing steps create a plurality of conductive traces including a first conductive trace and a second conductive trace within a conductive layer of the circuit board, wherein a first thickness of the first conductive trace from a surface of the first insulating layer is different than a second thickness of the second conductive trace from the surface, and laminating a second insulating layer over the conductive layer.
- Dell Products L.P.
- G06F1/18
- CPC G06F1/184
- Dell products l.p.
- G06F3/06
- CPC G06F3/0604
- CPC G06F3/0616
- G06F9/445
- CPC G06F9/44505
- G06F9/455
- G06F9/50
- G06F13/42
- CPC G06F9/45558
- G06N10/40
- G06N10/60
- CPC G06F9/5027
- CPC G06F9/505
- G06F11/14
- CPC G06F11/1446
- G06F11/22
- CPC G06F11/2273
- G06F11/30
- G06F11/34
- CPC G06F11/3034
- G06F12/0802
- CPC G06F12/0802
- G06F12/0831
- G06F12/0882
- G06F12/0891
- CPC G06F12/0835
- CPC G06F12/0848
- G06F13/20
- G06F15/82
- CPC G06F13/20
- G06F1/20
- G06F13/40
- CPC G06F13/4221
- G06N3/08
- CPC G06N3/08
- G06N10/20
- G06F17/16
- CPC G06N10/20
- CPC G06N10/40
- G06N20/00
- CPC G06N20/00
- H01L23/00
- H01L21/48
- H01L23/49
- H01L23/498
- CPC H01L24/13
- H05K1/02
- H05K1/11
- H05K1/18
- H05K3/00
- H05K3/04
- H05K3/34
- CPC H05K1/0284
- CPC H05K1/111
- H05K3/46
- H05K3/24
- CPC H05K3/4655