Category:Kuo-Cheng Chiang

Kuo-Cheng Chiang

Executive Summary

Kuo-Cheng Chiang is an inventor who has filed 7 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (5 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (5 patents), {using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate} (4 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Co., Ltd. (7 patents). Their most frequent collaborators include (5 collaborations), (4 collaborations), (3 collaborations).

Patent Filing Activity

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Technology Areas

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List of Technology Areas

• H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 4 patents
• H01L21/02603 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/66742 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/78618 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L27/0924 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/41733 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/02532 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/30604 (Chemical or electrical treatment, e.g. electrolytic etching (to form insulating layers): 2 patents
• H01L21/76897 ({Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step (self-aligned silicidation on field effect transistors): 2 patents
• H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 2 patents
• H01L29/45 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/66553 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 2 patents
• H01L21/823871 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L21/823807 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L21/823814 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/823842 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/32134 ({by liquid etching only}): 1 patents
• H01L21/823821 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/42372 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/02576 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/02579 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/31111 ({by chemical means}): 1 patents
• H01L29/66636 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/28518 (from a gas or vapour, e.g. condensation): 1 patents
• H01L21/823412 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823431 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/0665 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/6656 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
• H01L29/66818 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/7851 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L27/0886 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/823437 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823481 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/0262 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/6653 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
• H01L21/76805 ({the opening being a via or contact hole penetrating the underlying conductor}): 1 patents
• H01L21/76871 ({Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers}): 1 patents
• H01L21/76895 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/823828 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L23/53257 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/535 (including internal interconnections, e.g. cross-under constructions {(internal lead connections): 1 patents

Companies

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List of Companies

• Taiwan Semiconductor Manufacturing Co., Ltd.: 7 patents

Collaborators

• Chih-Hao Wang (5 collaborations)
• Shi Ning Ju (4 collaborations)
• Kuan-Lun Cheng (3 collaborations)
• Lung-Kun Chu (2 collaborations)
• Mao-Lin Huang (2 collaborations)
• Guan-Lin Chen (2 collaborations)
• Jia-Chuan You (2 collaborations)
• Wei-Hao Wu (1 collaborations)
• Chung-Wei Hsu (1 collaborations)
• Jia-Ni Yu (1 collaborations)
• Chih-Chao Chou (1 collaborations)
• Wen-Ting Lan (1 collaborations)
• Jui-Chien Huang (1 collaborations)
• Shih-Cheng Chen (1 collaborations)
• Zhi-Chang Lin (1 collaborations)
• Jung-Hung Chang (1 collaborations)
• Lo-Heng Chang (1 collaborations)
• Chia-Hao Chang (1 collaborations)
• Kuan-Ting Pan (1 collaborations)
• Chia-Hao Wang (1 collaborations)