CXMT CORPORATION patent applications on February 27th, 2025
Patent Applications by CXMT CORPORATION on February 27th, 2025
CXMT CORPORATION: 17 patent applications
CXMT CORPORATION has applied for patents in the areas of H10B12/00 (8), H03K19/20 (4), G11C11/4076 (3), H01L29/06 (2), G06F11/07 (1) H10B12/315 (3), H10B12/482 (3), G11C11/4076 (2), G06F11/0793 (1), G06F11/106 (1)
With keywords such as: signal, structure, control, circuit, direction, memory, command, layer, substrate, and semiconductor in patent application abstracts.
Patent Applications by CXMT CORPORATION
Inventor(s): Kai SUN of Hefei (CN) for cxmt corporation, Zequn HUANG of Hefei (CN) for cxmt corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0793
Abstract: provided are a storage system, a memory chip, and an error check and scrub method. the storage system includes a memory controller and a memory chip. the memory chip performs an error check and scrub ecs operation on a memory array; and sends a generated ecs finish flag signal to the memory controller after a current ecs operation is completed. the memory controller receives the ecs finish flag signal, and sends a generated ecs start flag signal to the memory chip based on the ecs finish flag signal, so that the memory chip enters a new ecs operation cycle.
Inventor(s): Zequn HUANG of Hefei (CN) for cxmt corporation, Kai SUN of Hefei (CN) for cxmt corporation
IPC Code(s): G06F11/10, G11C11/406, G11C11/4076, H03K19/20
CPC Code(s): G06F11/106
Abstract: provided are a control circuit, a control method, and a semiconductor memory. the control circuit includes a timing control module and a command control module. an output terminal of the timing control module is connected to an input terminal of the command control module. the timing control module is configured to receive a first clock signal, perform counting based on the first clock signal, generate an error check and scrub (ecs) flag signal, and send the ecs flag signal to the command control module. the ecs flag signal is in a valid state when a counting value meets a preset condition. the command control module is configured to receive the ecs flag signal, obtain a refresh command signal when the ecs flag signal is in the valid state, and generate an ecs command signal based on the refresh command signal.
20250069645. CONTROL CIRCUIT, CONTROL METHOD, AND MEMORY_simplified_abstract_(cxmt corporation)
Inventor(s): Zhiqiang ZHANG of Hefei (CN) for cxmt corporation
IPC Code(s): G11C11/4076, G11C11/408, H03K19/20
CPC Code(s): G11C11/4076
Abstract: provided are a control circuit, a control method, and a memory. the control circuit includes: an input control circuit, configured to generate a first drive control signal and a second drive control signal based on a command/address control signal and a command/address inversion signal; an input processing circuit, configured to generate a first intermediate command/address signal based on the first drive control signal and the second drive control signal when the command/address control signal is in an enabled state, that the circuit is in a power down mode being indicated when the command/address control signal is in the enabled state; and a logic decoding circuit, configured to generate a power down mode exit signal in the power down mode based on the command/address inversion signal and the first intermediate command/address signal.
20250069646. CONTROL CIRCUIT, CONTROL METHOD, AND MEMORY_simplified_abstract_(cxmt corporation)
Inventor(s): Zhiqiang ZHANG of Hefei (CN) for cxmt corporation
IPC Code(s): G11C11/4076, H03K19/20
CPC Code(s): G11C11/4076
Abstract: provided are a control circuit, a control method, and a memory. the control circuit includes: a flag signal generation circuit, configured to generate a command/address inversion flag signal based on a command/address control signal and an initial inversion flag signal; an input processing circuit, configured to generate a first intermediate command/address signal based on the command/address control signal and an initial command/address signal; and a logic decoding circuit, configured to: receive the first intermediate command/address signal and the command/address inversion flag signal, and generate a power down mode entry signal or a power down mode exit signal based on the command/address inversion flag signal and the first intermediate command/address signal.
Inventor(s): Jia WANG of Hefei (CN) for cxmt corporation
IPC Code(s): G11C11/4096, G11C11/4094, H03K19/20
CPC Code(s): G11C11/4096
Abstract: provided are a read/write circuit, a read/write method, and a memory. the read/write circuit includes: a write driver circuit, configured to: precharge a data line, and write to-be-written data into the data line; and a control circuit, when in a mask write mode, the control circuit being configured to control the write driver circuit to stop precharging the data line after data read and before data write, and when not in the mask write mode, the control circuit being configured to control the write driver circuit to precharge the data line before data write.
20250069672. COLUMN CONTROL CIRCUITS AND STORAGE DEVICES_simplified_abstract_(cxmt corporation)
Inventor(s): Zijian WANG of Hefei (CN) for cxmt corporation
IPC Code(s): G11C16/32, G11C16/04, G11C16/26
CPC Code(s): G11C16/32
Abstract: provided are a column control circuit and a memory device. the column control circuit includes a delay control circuit and a control signal generation circuit. the delay control circuit receives a column selection start signal, and generates and outputs a column selection end signal. the column selection end signal has a first delay amount relative to the column selection start signal. the control signal generation circuit receives the column selection start signal, the column selection end signal, and a target bank group selection signal, and generates and outputs a target column selection start signal, a target column selection window signal, and a target column selection end signal. the target column selection window signal has a second delay amount relative to the column selection start signal, the second delay amount is less than or equal to the first delay amount.
20250069681. MEMORY_simplified_abstract_(cxmt corporation)
Inventor(s): Jia WANG of Hefei (CN) for cxmt corporation
IPC Code(s): G11C29/56
CPC Code(s): G11C29/56008
Abstract: a memory is disclosed. an input terminal of a compression circuit receives read data transmitted through transmission paths of multiple data input/output pins, and the compression circuit separately compresses the read data transmitted through the transmission paths of the data input/output pins. a first input terminal of a data input/output selector is connected to an output terminal of the compression circuit, and the data input/output selector receives multiple pieces of compressed data, and is configured to: in a test mode, transmit the multiple pieces of compressed data to any one of the multiple data input/output pins.
Inventor(s): Chih-Cheng LIU of Hefei (CN) for cxmt corporation
IPC Code(s): H01L23/00, H01L21/768, H01L23/48
CPC Code(s): H01L24/05
Abstract: provided are a semiconductor interconnection structure, which includes a base, multiple independent conductive pillars, and a first conductive connection pad. the base has a first surface and a second surface. the multiple independent conductive pillars are disposed in the base. the first conductive connection pad is disposed on the first surface of the base and includes a mesh structure, and the mesh structure includes multiple first nodes. each of the first nodes is connected to a first end of one or first ends of more of the conductive pillars, or a first end of each of the conductive pillars is connected to one or more of the first nodes. first ends of all the conductive pillars are interconnected through the first conductive connection pad. the semiconductor interconnection structure has good heat dissipation performance and mechanical performance.
Inventor(s): Meng HUANG of Hefei (CN) for cxmt corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: the semiconductor structure includes: a plurality of active areas, each one of the plurality of active areas having a first end portion and a second end portion opposite to each other along a third direction, where the second end portion has a first part and a second part and a third part connecting one end of the first part and one end of the second part; a plurality of bit lines extending along a second direction and each connected to a plurality of active areas in the same layer; a plurality of word lines extending along a first direction and each connected to a plurality of active areas in the same column; and a plurality of memory structures, each one of the plurality of memory structures covering part of a surface of the second end portion and filling a gap between the first part and the second part.
Inventor(s): Qinghua HAN of Hefei City, Anhui Province (CN) for cxmt corporation, Kanyu CAO of Hefei City, Anhui Province (CN) for cxmt corporation, Xiang LIU of Hefei City, Anhui Province (CN) for cxmt corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: the present disclosure relates to a semiconductor structure and a method for manufacturing the same. the semiconductor structure includes a substrate, a plurality of word lines, and a plurality of repeating units. the plurality of word lines are spaced apart in parallel on the substrate, the plurality of word lines extending along a first direction; the plurality of repeating units are respectively located in gaps between adjacent word lines, each of the plurality of repeating units including an active structure and an air gap structure arranged side by side in a second direction. the second direction intersects with the first direction.
Inventor(s): Chao LIN of Hefei (CN) for cxmt corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/315
Abstract: provided are a semiconductor structure, a method for manufacturing same, and a memory. the semiconductor structure includes the following: a substrate; multiple transistor groups located on the substrate and arranged in an array, where each transistor group includes a first transistor and a second transistor; and the first transistor and the second transistor each include: a channel region; a source and a drain located at two opposite ends of the channel region; and a gate located on a side, in two opposite sides of the channel region, away from another transistor; and multiple connection structures located between a channel region of the first transistor and a channel region of the second transistor, where the channel region of the first transistor is connected to the channel region of the second transistor by the connection structure.
Inventor(s): Mengmeng YANG of Hefei (CN) for cxmt corporation, Yi TANG of Hefei (CN) for cxmt corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: disclosed are a semiconductor structure and a method for manufacturing the semiconductor structure. the semiconductor structure includes a base substrate provided thereon with stacks and first isolation layers alternately arranged in a first direction. the stack includes active structures and second isolation layers alternately arranged in a third direction. the active structure is provided with two first recesses therein. in the third direction, a thickness of the first recess is the same as a thickness of the active structure. the active structure is provided with one capacitor on each of opposite sides thereof, and the capacitor includes an upper electrode, a dielectric layer, and a lower electrode. the lower electrode is located on an inner wall of the first recess. the upper electrode is located between two adjacent stacks and is arranged opposite to the first recess, and the upper electrode also penetrates through the first isolation layer.
Inventor(s): Hong WANG of Hefei (CN) for cxmt corporation, Xiaojie LI of Hefei (CN) for cxmt corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: provided are a semiconductor structure and a method of manufacturing the same. the method of manufacturing a semiconductor structure includes the following steps: a substrate and a stacked structure located on the substrate are provided, the stacked structure including first insulating layers and semiconductor layers alternately stacked along the vertical direction, and the stacked structure having a first region; parts of the stacked structure in the first region are etched to form multiple first trenches arranged at intervals and multiple first staircase regions located between the first trenches; second insulating layers are formed in the first trenches; the stacked structure in the multiple first staircase regions is etched along the vertical direction to form a first staircase structure; conductive layers are formed at the top of the first staircase structure; and the semiconductor layers under the conductive layers are removed.
Inventor(s): Mengmeng YANG of Hefei (CN) for cxmt corporation, Yi TANG of Hefei (CN) for cxmt corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/482
Abstract: a semiconductor structure includes a substrate, a stacked structure, a signal line group, and a first staircase structure. the stacked structure is located on the substrate, and includes multiple storage layers arranged at intervals in a first direction, and each storage layer includes multiple memory cells arranged at intervals in a second direction. the signal line group includes multiple signal lines arranged at intervals in the first direction, and each signal line is electrically connected to the memory cells. the first staircase structure includes first stairs electrically connected to the signal lines, each first stair protrudes from a corresponding signal line in a third direction, and projections of the multiple first stairs on a top surface of the substrate are arranged in the second direction.
Inventor(s): Yexiao YU of Hefei (CN) for cxmt corporation, HONG MA of Hefei (CN) for cxmt corporation, Zhongming LIU of Hefei (CN) for cxmt corporation
IPC Code(s): H10B12/00, H01L21/311, H01L23/528
CPC Code(s): H10B12/482
Abstract: a semiconductor structure includes a substrate and a first bit line pillar. the first bit line pillar is located on the substrate, and includes a first dielectric layer, a first insulating layer, and a first contact layer that are successively stacked in a thickness direction of the substrate. the first insulating layer is adjacent to the substrate and has a first preset thickness. the first preset thickness is associated with a thickness sum of the first dielectric layer, the first insulating layer, and the first contact layer. a ratio of a length of a top surface of the first insulating layer in a first direction to a length of a bottom surface of the first insulating layer in the first direction is a first target value. the first direction, the top surface and the bottom surface of the first insulating layer are all perpendicular to the thickness direction.
20250071981. MEMORY AND STORAGE SYSTEM_simplified_abstract_(cxmt corporation)
Inventor(s): Yanzhe TANG of Hefei (CN) for cxmt corporation
IPC Code(s): H10B12/00, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H10B12/50
Abstract: provided are a memory and a storage system. the memory includes: a substrate; a control circuit layer located in the substrate, the control circuit layer including a part of control circuits of the memory; and at least two storage structure layers sequentially stacked on the control circuit layer in a first direction. the first direction is perpendicular to the surface of the substrate. the storage structure layer is connected to the control circuit layer. the storage structure layer includes memory cells arranged in an array. the memory cell includes a storage structure and at least two series-connected selection transistors connected to the storage structure. the at least two series-connected selection transistors are stacked in the first direction. a channel structure of the selection transistor includes at least one layer of nanosheets. the at least two series-connected selection transistors share one gate structure.
Inventor(s): Sijia LI of Hefei City (CN) for cxmt corporation, Yi TANG of Hefei City (CN) for cxmt corporation
IPC Code(s): H10B43/27, H01L21/762, H01L29/06, H10B41/27
CPC Code(s): H10B43/27
Abstract: a method for forming a semiconductor structure includes: forming a stack structure of alternately stacked dielectric layers and semiconductor layers on a substrate; forming isolation structures penetrating through the stack structure, and extending into the substrate, where the isolation structures separate the stack structure into sub-stack structures; forming word line openings extending along a third direction in each of the isolation structures, where a bottom surface of each of the word line openings is lower than a bottom surface of a semiconductor layer closest to the substrate, and each of the word line openings is located between one of the sub-stack structures and one of the isolation structures; forming an insulating structure between each of the word line openings and the substrate; and forming a word line structure in each of the word line openings.
- CXMT CORPORATION
- G06F11/07
- CPC G06F11/0793
- Cxmt corporation
- G06F11/10
- G11C11/406
- G11C11/4076
- H03K19/20
- CPC G06F11/106
- G11C11/408
- CPC G11C11/4076
- G11C11/4096
- G11C11/4094
- CPC G11C11/4096
- G11C16/32
- G11C16/04
- G11C16/26
- CPC G11C16/32
- G11C29/56
- CPC G11C29/56008
- H01L23/00
- H01L21/768
- H01L23/48
- CPC H01L24/05
- H10B12/00
- CPC H10B12/315
- CPC H10B12/33
- CPC H10B12/482
- H01L21/311
- H01L23/528
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/786
- CPC H10B12/50
- H10B43/27
- H01L21/762
- H10B41/27
- CPC H10B43/27
