Avago Technologies International Sales Pte. Limited patent applications on May 1st, 2025
Patent Applications by Avago Technologies International Sales Pte. Limited on May 1st, 2025
Avago Technologies International Sales Pte. Limited: 27 patent applications
Avago Technologies International Sales Pte. Limited has applied for patents in the areas of H03M1/46 (2), H03F3/19 (2), G06F3/06 (2), H03H9/13 (2), H03H9/02 (2) H03F3/19 (2), G01S7/4873 (1), H03H9/605 (1), H04W24/10 (1), H04N19/423 (1)
With keywords such as: signal, circuit, third, device, coupled, output, configured, frequency, circuitry, and based in patent application abstracts.
Patent Applications by Avago Technologies International Sales Pte. Limited
Inventor(s): Reinhard Enne of Hofstetten-Gruenau AT for avago technologies international sales pte. limited, Milos Davidovic of Vienna AT for avago technologies international sales pte. limited, Wolfgang Gaberl of Vienna AT for avago technologies international sales pte. limited
IPC Code(s): G01S7/487, G01S7/4865, H03M1/36
CPC Code(s): G01S7/4873
Abstract: the subject technology is directed to light detection and ranging (lidar) systems and methods. in an embodiment, the subject technology provides a device comprising an optical module configured to receive a first optical signal and a first circuit configured to generate a first electrical signal based on the first optical signal. the device also comprises a first comparator configured to generate a second electrical signal by comparing the first electrical signal to a first threshold value. the device further comprises a first filter configured to generate a first pulse based on the second electrical signal. the first pulse comprises a first point associated with a first timestamp. the timestamp data may be briefly retained in the analog domain, followed by subsequent digital conversion, allowing for significant power savings and reduced system bandwidth. there are other embodiments as well.
Inventor(s): Arun Prakash Jana of Bangalore IN for avago technologies international sales pte. limited
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0604
Abstract: solutions for managing raid logical devices. some solutions provide enhanced online capacity expansion for virtual disks on raid drives, for example by taking advantage of the hardware capabilities to expand a virtual disk stripe by stripe. some solutions provide increase hardware automation, which can reduce firmware load and/or provide more efficient input-output operations (io) for the online capacity expansion operation.
Inventor(s): Arun Prakash Jana of Bangalore IN for avago technologies international sales pte. limited
IPC Code(s): G06F3/06
CPC Code(s): G06F3/061
Abstract: solutions for managing raid virtual disks. some solutions enable increased use of hardware circuitry to schedule and perform io on a virtual drive, providing for more efficient io. in some cases, this can be accomplished by notifying the hardware of precise regions of a virtual disk affected by the maintenance operation and any given time. the hardware then, can continue to perform host io on portions of the logical disk not undergoing maintenance.
Inventor(s): Ronen Vainish of Sunnyvale CA US for avago technologies international sales pte. limited
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/4401
Abstract: novel systems and methods for canvas sanitization are provided. in various embodiments, a system and method include: receiving a request to open a web page from a client device; replacing, via an agent, a first function with a second function, the agent being loaded to a browser; loading the web page from a web server to the browser; in response to an attempt to perform the first function on the web page, performing, via the browser, the second function corresponding to the first function to generate a drawing for a predetermined period of time; converting, via the agent, the drawing to an image; and transmitting the image to the client device. other aspects, embodiments, and features are also claimed and described.
Inventor(s): Darren Neuman of Palo Alto CA US for avago technologies international sales pte. limited, Flaviu Dorin Turean of Palo Alto CA US for avago technologies international sales pte. limited, Friederich Mombers of San Jose CA US for avago technologies international sales pte. limited
IPC Code(s): G06F12/1045, G06F12/1009, G06F13/16
CPC Code(s): G06F12/1045
Abstract: an mmu with prefetch functionality is provided. the mmu includes a first tlb, burst buffer, second tlb and control logic. the first tlb is configured to fetch a first set of one or more first page table entries based, at least in part, on a virtual address, and before a request to access a client address is received from a client. the burst buffer stores a plurality of second page table entries from a respective page table associated with a first page table address. a second translation lookaside buffer is configured to fetch a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer based, at least in part, on the virtual address, and before the request to access a client address is received from the client.
Inventor(s): Kin Wai Roy Chew of Singapore SG for avago technologies international sales pte. limited
IPC Code(s): G11B5/48
CPC Code(s): G11B5/4826
Abstract: a circuit for determining head gimbal assembly (hga) height is provided. the circuit includes a first switch configured to be controlled by a first clock signal, an amplifier, and a first capacitor coupled to the first switch, wherein the first capacitor is formed by at least part of a head gimbal assembly and a storage media. the circuit further includes a second capacitor coupled to an input of the amplifier, and an output of the amplifier, wherein the second capacitor is configured to store a charge from the first capacitor over one or more cycles of the first clock signal. the amplifier is configured to generate an output voltage based, at least in part, on a change in the capacitance of the first capacitor over the one or more cycles of the first clock signal.
Inventor(s): Sam Zhao of Irvine CA US for avago technologies international sales pte. limited, Xiaoming Li of Newport Beach CA US for avago technologies international sales pte. limited, Qing Liu of Irvine CA US for avago technologies international sales pte. limited
IPC Code(s): H01L23/528, H01L23/14, H01L23/48
CPC Code(s): H01L23/5286
Abstract: novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a backside power distribution network. in various embodiments, an apparatus includes a first substrate comprising a device configured to receive a voltage and a first side located on a front side of the first substrate and a second side located on a back side of the first substrate, a second substrate, the second substrate configured to support the first substrate, and a power distribution network located at an interface between the second side of the first substrate and the second substrate.
Inventor(s): Seyed Mehrdad Babamir of San Diego CA US for avago technologies international sales pte. limited
IPC Code(s): H01P5/16, H04B1/40
CPC Code(s): H01P5/16
Abstract: wide-band output isolation is provided. a device includes a first output for a first radio frequency (rf) signal. a device includes a second output for a second rf signal. the device includes a first transistor having a first source/drain. the device includes a second transistor having a first source/drain, wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor and wherein the first and second transistors are disposed between the first output and the second output.
Inventor(s): Sukeshwar Kannan of San Jose CA US for avago technologies international sales pte. limited, Sheng Zhang of Cupertino CA US for avago technologies international sales pte. limited, Near Margalit of Westlake Village CA US for avago technologies international sales pte. limited
IPC Code(s): H01S5/0233
CPC Code(s): H01S5/0233
Abstract: novel tools and techniques are provided for implementing a semiconductor or optical engine package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package including a dummy die coupled to a top surface of a fan-out wafer comprising an electronic die and coupled to a side of a photonic die. in various embodiments, an apparatus includes a first layer comprising an electronic die. a photonic die can be stacked on and coupled to the electronic die and a dummy die can be coupled to a first side of the photonic die and coupled to the first layer.
Inventor(s): Seyed Mehrdad Babamir of San Diego CA US for avago technologies international sales pte. limited
IPC Code(s): H03F3/19
CPC Code(s): H03F3/19
Abstract: wide-band matching in out-of-band blocker rejection filters is provided. a device includes a first inductor. the device includes a second inductor magnetically coupled with the first inductor and with an amplifier. the device includes a notch filter electrically coupled between the first inductor and the second inductor. the amplifier can be configured to amplify a plurality of radio frequency signals. a bandwidth of the radio frequency signals can exceed 1.5 gigahertz (ghz).
Inventor(s): Seyed Mehrdad Babamir of San Diego CA US for avago technologies international sales pte. limited, Ali Afsahi of San Diego CA US for avago technologies international sales pte. limited
IPC Code(s): H03F3/19, H01P5/16
CPC Code(s): H03F3/19
Abstract: wide-band output isolation is provided. a device includes a first output for a first radio frequency (rf) signal. a device includes a second output for a second rf signal. the device includes a first transistor having a first source/drain. the device includes a second transistor having a first source/drain, wherein the first source/drain of the first transistor is coupled to the first source/drain of the second transistor and wherein the first and second transistors are disposed between the first output and the second output.
Inventor(s): Dae Hyun Kwon of San Diego CA US for avago technologies international sales pte. limited, Ali Afsahi of San Diego CA US for avago technologies international sales pte. limited
IPC Code(s): H03F3/24, H03F3/189
CPC Code(s): H03F3/24
Abstract: a device to receive a first signal from a driver. the device comprising a first circuit, a second circuit, a third circuit, and a fourth circuit. the first circuit to provide a second signal having a first level. the second circuit to detect the first level of the first signal and to provide a third signal to control a third circuit of the device. the third circuit to provide a fourth signal, the fourth signal having a first level in response to a difference being smaller than a predetermined value, and the fourth signal having a second level in response to the difference being larger than the predetermined value. the fourth circuit to provide a fifth signal, the fifth signal having a first level based at least on the second signal, and the fifth signal having a second level based at least on the second signal and the fourth signal.
Inventor(s): Guansheng Li of Irvine CA US for avago technologies international sales pte. limited, Jerry Jifang Han of Cupertino CA US for avago technologies international sales pte. limited, Bo Zhang of Irvine CA US for avago technologies international sales pte. limited, Delong Cui of Tustin CA US for avago technologies international sales pte. limited, Jun Cao of Irvine CA US for avago technologies international sales pte. limited
IPC Code(s): H03F3/60, H03G3/20
CPC Code(s): H03F3/605
Abstract: an amplifier includes a first transmission line from a first terminal to a second terminal. the first transmission line is characterized by a first characteristic impedance matched to a resistance of a source from which a first signal is coupled to the second terminal. the amplifier includes a first resistor with a first resistance and a second resistor with a second resistance coupled between the second terminal and a third terminal. the first resistance and the second resistance are adjustable to match an input impedance at the second terminal to the first characteristic impedance and to tune a gain of a second signal at the third terminal over the first signal at the second terminal. the amplifier includes a second transmission line from the third terminal to a third resistor with a third resistance, the second transmission line being characterized by a second characteristic impedance matched to the third resistance.
Inventor(s): JeaShik Shin of Hwaseong-si Gyeonggi-do KR for avago technologies international sales pte. limited, Hyeonhyeong Choe of Seoul KR for avago technologies international sales pte. limited, Jeesu Kim of San Ramon CA US for avago technologies international sales pte. limited
IPC Code(s): H03H7/01, H03H9/02
CPC Code(s): H03H7/0161
Abstract: a filter device for multi-band wireless communication includes a first circuit characterized by a first pass-band from a first frequency to a second frequency; a second circuit characterized by a second pass-band from a frequency no smaller than the first frequency to a third frequency, the third frequency being no higher than the second frequency but higher than the first frequency; a third circuit characterized by a third pass-band from a fourth frequency to a frequency no greater than the second frequency, the fourth frequency being no smaller than the first frequency but smaller than the second frequency; and a switch configured to connect the first circuit either to the second circuit to reconfigure a first filter with the second pass-band or to the third circuit to reconfigure a second filter with the third pass-band.
Inventor(s): Stephan Marksteiner of München DE for avago technologies international sales pte. limited, Winfried Nessler of München DE for avago technologies international sales pte. limited, Andriy Yatsenko of Vaterstetten DE for avago technologies international sales pte. limited
IPC Code(s): H03H9/13, H03H9/02, H03H9/17
CPC Code(s): H03H9/132
Abstract: the subject technology is related to acoustic resonators. more specifically, an embodiment of the subject technology provides an acoustic resonator device that includes a piezoelectric layer disposed between a first electrode and a second electrode. the total thickness of the first electrode, the second electrode, and the third electrode allows the device to operate according to a second (or higher order) thickness extension mode. there are other embodiments as well.
Inventor(s): Andriy Yatsenko of Vaterstetten DE for avago technologies international sales pte. limited, Winfried Nessler of München DE for avago technologies international sales pte. limited, Stephan Marksteiner of München DE for avago technologies international sales pte. limited, Alberto Hueltes of Pentling DE for avago technologies international sales pte. limited
IPC Code(s): H03H9/60, H03H9/13, H03H9/205
CPC Code(s): H03H9/605
Abstract: the subject technology is directed to acoustic filter systems and methods. in an embodiment, the subject technology provides a first resonator, a second resonator, and a third resonator. the first resonator comprises a first layer coupled to and positioned between a first electrode and a second electrode. the second resonator is coupled to the first resonator at a first node. the third resonator is coupled to the first node and a ground terminal. the third resonator comprises a second layer coupled to and positioned between a third electrode and a fourth electrode. depending on the implementation, each resonator may be associated with one or more thickness extension (te) modes and the device can function in high-frequency ranges (e.g., greater than 5 ghz) with low insertion loss. there are other embodiments as well.
Inventor(s): Delong Cui of Irvine CA US for avago technologies international sales pte. limited, Guansheng Li of Irvine CA US for avago technologies international sales pte. limited, Jun Cao of Irvine CA US for avago technologies international sales pte. limited, Yonghyun Shim of Irvine CA US for avago technologies international sales pte. limited, Yu-Ming Ying of Irvine CA US for avago technologies international sales pte. limited
IPC Code(s): H03K5/00, H03K19/20
CPC Code(s): H03K5/00006
Abstract: in some implementations, a circuitry may include a series of symmetrical stages with an initial stage in the series coupled to an input signal having a first plurality of phases and an output stage in the series coupling an output signal comprising a second plurality of phases to a calibration engine, where a quantity of the phases in the output signal is increased based at least on a quantity of the symmetrical stages and a quantity of the first plurality of the phases in the input signal. in addition, the circuitry may include implementations, where the calibration engine calibrates a frequency of the circuitry within a range based at least on a target frequency. the circuitry may include implementations, where the calibration engine outputs a current provided to the series, where the output current can be based at least on a calibrated frequency.
Inventor(s): Jie Fang of Austin TX US for avago technologies international sales pte. limited, Frank Singor of Austin TX US for avago technologies international sales pte. limited, Hongjie Zhu of Austin TX US for avago technologies international sales pte. limited, Chaoming Zhang of Austin TX US for avago technologies international sales pte. limited, Brian Caldona of Austin TX US for avago technologies international sales pte. limited
IPC Code(s): H03M1/12, H03M1/46
CPC Code(s): H03M1/121
Abstract: a system may include a first analog-to-digital converter (adc) of a first type electrically coupled by a plurality of switches to a plurality of adcs of a second type. the plurality of switches may be configured to select, based on a rate of an analog-to-digital conversion, a quantity of adcs of the second type, from among the plurality of adcs of the second type, to supply the analog-to-digital conversion at the rate. the plurality of switches may be configured to selectively bypass the first adc according to a resolution of the analog-to-digital conversion. the plurality of switches may be configured to bypass the first adc responsive to the resolution of the conversion being below a threshold.
Inventor(s): Chang Liu of Irvine CA US for avago technologies international sales pte. limited, Boyu Hu of Irvine CA US for avago technologies international sales pte. limited, Xiaoliang Li of Irvine CA US for avago technologies international sales pte. limited, Delong Cui of Tustin CA US for avago technologies international sales pte. limited, Jun Cao of Irvine CA US for avago technologies international sales pte. limited
IPC Code(s): H03M1/44
CPC Code(s): H03M1/44
Abstract: a system may include one or more receivers, circuitry, and a controller. each of the one or more receivers may include a plurality of analog-to-digital converters (adcs). each adc may measure a time relating to an analog-to-digital conversion by the adc, compare the time with a threshold, and generate, based on a result of the comparing, a first signal. the circuitry may be coupled to the one or more receivers. the circuitry may receive the first signal from each adc, determine, based at least on the first signal, characteristics of performance of each receiver, and output a plurality of second signals. each of the plurality of second signals may indicate the characteristics of performance of a corresponding receiver. the controller may be coupled to the circuitry and adjust a voltage provided to the one or more receivers, based at least on the plurality of second signals received from the circuitry.
Inventor(s): Hongjie Zhu of Austin TX US for avago technologies international sales pte. limited, Jie Fang of Austin TX US for avago technologies international sales pte. limited, Queennie Lim of San Jose CA US for avago technologies international sales pte. limited, Frank Singor of Austin TX US for avago technologies international sales pte. limited
IPC Code(s): H03M1/46, H03M1/00
CPC Code(s): H03M1/468
Abstract: a unit capacitor for a switched-capacitor digital-to-analog converter is provided. an apparatus includes a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. the apparatus further includes a second plate formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction. each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.
Inventor(s): Yong Liu of Irvine CA US for avago technologies international sales pte. limited, Xi Yang of Irvine CA US for avago technologies international sales pte. limited, Xiaochen Yang of irvine CA US for avago technologies international sales pte. limited, Jun Cao of Irvine CA US for avago technologies international sales pte. limited
IPC Code(s): H03M1/50, H03M1/10
CPC Code(s): H03M1/508
Abstract: a device may include an oscillator and a driver. the oscillator may be coupled to circuitry providing calibration of the oscillator. the oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (adc). the driver may be coupled to the oscillator and the adc. the driver may receive the second signal from the oscillator. the driver may receive a third signal indicating an amplitude to apply to the second signal. the driver may provide, to the adc based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.
Inventor(s): Jacob K. Easter of Fort Collins CO US for avago technologies international sales pte. limited, Doug Spannring of Fort Collins CO US for avago technologies international sales pte. limited
IPC Code(s): H03M1/68
CPC Code(s): H03M1/682
Abstract: a device may include a digital-to-analog converter (dac), including a current source, circuitry to mirror the current source, the circuitry including a transistor coupled to the current source, and a plurality of output paths, each output path of the plurality of output paths including a first switch to selectively configure a first transistor to mirror the current source, wherein each output path corresponds to a value of a respective bit of a first digital signal, and a plurality of cells, each cell of the plurality of cells including a second switch to selectively couple a second transistor to a corresponding one of the plurality of output paths, wherein each of the plurality of cells corresponds to a value of a respective bit of a second digital signal.
Inventor(s): Xiaochen Yang of Irvine CA US for avago technologies international sales pte. limited, Yong Liu of Irvine CA US for avago technologies international sales pte. limited, Renfei Liu of Rancho Santa Margarita CA US for avago technologies international sales pte. limited, Chifeng Wang of Irvine CA US for avago technologies international sales pte. limited, Delong Cui of Irvine CA US for avago technologies international sales pte. limited, Jun Cao of Irvine CA US for avago technologies international sales pte. limited
IPC Code(s): H04B1/04, H03F1/32
CPC Code(s): H04B1/0475
Abstract: in some implementations, the circuitry may include a circuit configured to receive a baseband signal, the baseband signal having an intermodulated non-linear distorted portion and a harmonic distorted portion. in addition, the circuitry may include a compensator coupled to the circuit, the compensator configured to generate a value to compensate for the intermodulated non-linear distorted portion without compensating for the harmonic distorted portion. the circuitry may include where the compensator is configured to output the value. the circuitry may include where the circuit is configured to adjust the baseband signal using the value. in some embodiments, the baseband signal can be baseband voltage. in some embodiments, the value can be a complex number.
Inventor(s): Gordon Li of San Diego CA US for avago technologies international sales pte. limited, Xuemin Chen of Rancho Santa Fe CA US for avago technologies international sales pte. limited
IPC Code(s): H04L43/08, G06N20/20, H04L41/083, H04L51/02
CPC Code(s): H04L43/08
Abstract: improved solutions that enable more effective and efficient communications with users, in particular with respect to field diagnostics and services. some solutions can enable users to better communicate with a provider to obtain more useful diagnostic and service information. certain solutions can employ multi-model switching machine learning techniques to enhance a user's communication with the provider and/or the provider's response.
Inventor(s): Minhua Zhou of San Diego CA US for avago technologies international sales pte. limited
IPC Code(s): H04N19/423, H04N19/105, H04N19/124, H04N19/176
CPC Code(s): H04N19/423
Abstract: a video decoder with in-loop memory bandwidth compression is provided. a video decoder includes a decoding logic configured to decode an encoded bitstream to generate a reference block of video data, and a memory bandwidth compression logic configured to compress the reference block of video data based on a selection between a first compression algorithm, second compression algorithm, or to copy the reference block without compression. selection is based on at least one of the first block size, second block size, or uncompressed block size. the selected block is written to an off-chip memory, and a compression algorithm indicator associated with the selected block is written to an on-chip memory.
Inventor(s): Srinath Puducheri Sundaravaradhan of Sunnyvale CA US for avago technologies international sales pte. limited, Ron Porat of San Diego CA US for avago technologies international sales pte. limited, Karim Nassiri Toussi of San Mateo CA US for avago technologies international sales pte. limited
IPC Code(s): H04W24/10, H04W48/08
CPC Code(s): H04W24/10
Abstract: the disclosure describes systems and methods for downlink channel sounding in multi-access point (multi-ap) networks. the system can be configured to provide one or more sounding options. in joint sounding options, stations can measure the combined downlink channel from all the aps and can provide feedback on the composite channel. in individual sounding options, stations can measure the downlink channel from each ap separately and can provide feedback on the individual channels. in implicit sounding options, each ap can estimate the uplink channel transmitted by the stations. the uplink channel information can then be used to derive the corresponding downlink channel.
Inventor(s): Debopriyo Chowdhury of San Diego CA US for avago technologies international sales pte. limited, Mahnaz Atri of San Diego CA US for avago technologies international sales pte. limited, Ali Afsahi of San Diego CA US for avago technologies international sales pte. limited
IPC Code(s): H04W52/36, H04B17/318
CPC Code(s): H04W52/367
Abstract: a device comprising a first circuit, a second circuit, and a third circuit. the first circuit to receive, from an amplifier, a first signal having a first amount of power. the first circuit to also determine, based on the first amount of power, a range of power associated with transmission of the first signal by a transmitter. the second circuit to receive a second signal to define one or more characteristics of the second circuit. receipt of the second signal, by the second circuit, can cause the second circuit to adjust the first signal from the first amount of power to a second amount of power. the third circuit to receive, from the second circuit, the first signal having the second amount of power, and the third circuit to provide a third signal having a voltage level to indicate a third amount of power transmitted by the transmitter.
Avago Technologies International Sales Pte. Limited patent applications on May 1st, 2025
- Avago Technologies International Sales Pte. Limited
- G01S7/487
- G01S7/4865
- H03M1/36
- CPC G01S7/4873
- Avago technologies international sales pte. limited
- G06F3/06
- CPC G06F3/0604
- CPC G06F3/061
- G06F9/4401
- CPC G06F9/4401
- G06F12/1045
- G06F12/1009
- G06F13/16
- CPC G06F12/1045
- G11B5/48
- CPC G11B5/4826
- H01L23/528
- H01L23/14
- H01L23/48
- CPC H01L23/5286
- H01P5/16
- H04B1/40
- CPC H01P5/16
- H01S5/0233
- CPC H01S5/0233
- H03F3/19
- CPC H03F3/19
- H03F3/24
- H03F3/189
- CPC H03F3/24
- H03F3/60
- H03G3/20
- CPC H03F3/605
- H03H7/01
- H03H9/02
- CPC H03H7/0161
- H03H9/13
- H03H9/17
- CPC H03H9/132
- H03H9/60
- H03H9/205
- CPC H03H9/605
- H03K5/00
- H03K19/20
- CPC H03K5/00006
- H03M1/12
- H03M1/46
- CPC H03M1/121
- H03M1/44
- CPC H03M1/44
- H03M1/00
- CPC H03M1/468
- H03M1/50
- H03M1/10
- CPC H03M1/508
- H03M1/68
- CPC H03M1/682
- H04B1/04
- H03F1/32
- CPC H04B1/0475
- H04L43/08
- G06N20/20
- H04L41/083
- H04L51/02
- CPC H04L43/08
- H04N19/423
- H04N19/105
- H04N19/124
- H04N19/176
- CPC H04N19/423
- H04W24/10
- H04W48/08
- CPC H04W24/10
- H04W52/36
- H04B17/318
- CPC H04W52/367