Astera Labs, Inc. patent applications on May 1st, 2025
Patent Applications by Astera Labs, Inc. on May 1st, 2025
Astera Labs, Inc.: 2 patent applications
Astera Labs, Inc. has applied for patents in the areas of G06F3/06 (1), H05K1/02 (1), H01L21/48 (1), H01L23/498 (1), H05K3/46 (1) G06F3/0664 (1), H05K1/0251 (1)
With keywords such as: data, values, pad, error, metadata, structures, configured, volumes, pluralities, and pads in patent application abstracts.
Patent Applications by Astera Labs, Inc.
20250138757. VIRTUAL METADATA STORAGE_simplified_abstract_(astera labs, inc.)
Inventor(s): Jitendra Mohan of Santa Clara CA US for astera labs, inc., Justina Provine of Fremont CA US for astera labs, inc., Anh T. Tran of Elk Grove CA US for astera labs, inc., Ken (Keqin) Han of Fremont CA US for astera labs, inc., Enrique Musoll of San Jose CA US for astera labs, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0664
Abstract: a decoding engine within an integrated-circuit (ic) component executes a first plurality of error detection/correction operations with respect to first and second pluralities of data volumes to generate a corresponding first and second pluralities of error syndrome values. each data volume of the first plurality of data volumes includes a first data block and a first error correction code together with a respective one of a plurality of unique q-bit metadata values, and each data volume of the second plurality of data volumes includes a second data block and a second error correction code together with a respective one of the plurality of unique q-bit metadata values. output circuitry within the decoding engine selects one of the plurality of q-bit metadata values to be an output q-bit metadata value according to error-count differentiation indicated by the first and second pluralities of error syndrome values.
Inventor(s): Long YANG of Pleasanton CA US for astera labs, inc., Liang XUE of Los Altos CA US for astera labs, inc., Changyu SUN of Fremont CA US for astera labs, inc., Aleksandr OYSGELT of Palo Alto CA US for astera labs, inc.
IPC Code(s): H05K1/02, H01L21/48, H01L23/498, H05K3/46
CPC Code(s): H05K1/0251
Abstract: an electronic system having a mounting substrate with a plurality of layers. the mounting substrate includes a plurality of layers having pad structures each configured with a pad within an anti-pad opening. the pad structures are connected with via. the pad structures are configured to reduce the impedance of the via by altering the shape, size, and position of the pads and the anti-pad openings. the pads of the pad structures are configured as functional and non-functional pads based on the impedance targets for the vias.