Applied materials, inc. (20250006499). INTEGRATED DIPOLE REGION FOR TRANSISTOR
INTEGRATED DIPOLE REGION FOR TRANSISTOR
Organization Name
Inventor(s)
Srinivas Gandikota of Santa Clara CA US
Steven C.H. Hung of Sunnyvale CA US
Tianyi Huang of Santa Clara CA US
Seshadri Ganguli of San Jose CA US
INTEGRATED DIPOLE REGION FOR TRANSISTOR
This abstract first appeared for US patent application 20250006499 titled 'INTEGRATED DIPOLE REGION FOR TRANSISTOR
Original Abstract Submitted
methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. the electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-� dielectric layer on the metal film. in some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-� dielectric layer on the interfacial layer, and a metal film on the high-� dielectric layer. in some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-� dielectric layer.