Applied materials, inc. (20240266414). MULTI-VT INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES simplified abstract

MULTI-VT INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES

Organization Name

applied materials, inc.

Inventor(s)

Srinivas Gandikota of Santa Clara CA (US)

Yixiong Yang of Fremont CA (US)

Tengzhou Ma of San Jose CA (US)

Tianyi Huang of Santa Clara CA (US)

Geetika Bajaj of Cupertino CA (US)

Hsin-Jung Yu of Santa Clara CA (US)

Seshadri Ganguli of Sunnyvale CA (US)

MULTI-VT INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240266414 titled 'MULTI-VT INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES

The patent application describes methods for manufacturing semiconductor devices with multi-vt capability in the scaled space between nanosheets in advanced GAA nodes. By combining n-/p-dipole and mid-gap metal with low resistance, gate resistance is reduced to achieve the desired work function and low-resistance metal gate.

• Integration scheme to reduce gate resistance
• Combination of n-/p-dipole and mid-gap metal
• Use of mid-gap metal as a liner for subsequent low resistance metal fill
• Filling nanosheets with a single work function mid-gap metal
• Achieving n and p work function with mid-gap metal
• Shifting bandedge with mid-gap materials after dipole engineering

Potential Applications: - Semiconductor manufacturing - Advanced GAA nodes technology - Electronics industry

Problems Solved: - Gate resistance reduction - Achieving desired work function - Enhancing multi-vt capability in semiconductor devices

Benefits: - Improved performance of semiconductor devices - Enhanced efficiency in manufacturing processes - Increased versatility in device design

Commercial Applications: Title: Advanced Semiconductor Manufacturing Technology for Enhanced Device Performance This technology can be applied in the production of high-performance semiconductor devices for various electronic applications, including smartphones, computers, and IoT devices. The innovation offers a competitive edge in the semiconductor industry by improving device performance and efficiency.

Questions about the technology: 1. How does the integration of n-/p-dipole and mid-gap metal reduce gate resistance in semiconductor devices? 2. What are the potential implications of using a single work function mid-gap metal to fill nanosheets in advanced GAA nodes?

Original Abstract Submitted

embodiments of the disclosure advantageously provide methods of manufacturing semiconductor devices having multi-vt capability in the scaled space between nanosheets in advanced gaa nodes. one or more embodiments provide an integration scheme to advantageously reduce the gate resistance by combining n-/p-dipole and mid-gap metal with low resistance to achieve desired work function and low-resistance metal gate. in one or more embodiments, a mid-gap metal is used to fill nanosheets and act as a liner for subsequent fill by a low resistance metal. after dipole engineering, instead of filling the gate-all-around nanosheet with traditional n or p metal, in one or more embodiments, the nanosheet is advantageously filled with a single work function mid-gap metal to achieve n and p work function. if the work function was shifted in either p-dipole or n-dipole bandedge after dipole engineering, the mid-gap materials can also shift the bandedge the opposite way.