Applied Materials, Inc. patent applications on March 6th, 2025
Patent Applications by Applied Materials, Inc. on March 6th, 2025
Applied Materials, Inc.: 36 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01L21/67 (7), H01L23/00 (5), H01J37/32 (5), H01L21/02 (4), G03F7/20 (3) H01J37/08 (2), G03F7/2051 (2), H01L24/05 (2), B23K26/3568 (1), H01L21/67242 (1)
With keywords such as: substrate, surface, include, layer, processing, structure, dielectric, device, flow, and chamber in patent application abstracts.
Patent Applications by Applied Materials, Inc.
Inventor(s): Chunrong YIN of Palo Alto CA (US) for applied materials, inc., Ching-Pao WANG of Hsinchu (TW) for applied materials, inc., Joseph LIU of Hsinchu City (TW) for applied materials, inc., Yixing LIN of Saratoga CA (US) for applied materials, inc., Boon Sen CHAN of Singapore (SG) for applied materials, inc., Siamak SALIMIAN of Los Altos CA (US) for applied materials, inc.
IPC Code(s): B23K26/352, B23K26/082, B23K26/40
CPC Code(s): B23K26/3568
Abstract: methods and apparatus for cleaning a used component from a substrate processing chamber are provided. in some embodiments, the method includes obtaining a used component having a ceramic base and process residue that is generated as a byproduct in the substrate processing chamber and that is in direct contact with the ceramic base; and at least partially removing the process residue by scanning a laser beam across the process residue.
20250073850. GAS AMPLIFIER FOR CMP COOLING_simplified_abstract_(applied materials, inc.)
Inventor(s): Haosheng WU of Fremont CA (US) for applied materials, inc., Shou-Sung CHANG of Mountain View CA (US) for applied materials, inc., Priscilla DIEP of San Jose CA (US) for applied materials, inc., Hui CHEN of San Jose CA (US) for applied materials, inc., Chih Chung CHOU of San Jose CA (US) for applied materials, inc., Jeonghoon OH of Saratoga CA (US) for applied materials, inc., Jianshe TANG of San Jose CA (US) for applied materials, inc., Brian J. BROWN of Palo Alto CA (US) for applied materials, inc.
IPC Code(s): B24B53/017, H01L21/306
CPC Code(s): B24B53/017
Abstract: a chemical mechanical polishing chamber may include a platen disposed within the chemical mechanical polishing chamber, the platen configured to support a polishing pad. the chamber may also include a slurry delivery arm configured to deliver a slurry to the polishing pad during a chemical mechanical polishing process. the chamber may include an arm may include one or more brackets, mechanically attached to an internal side of the chemical mechanical polishing chamber and positioned over the platen. the chamber may include a plurality of nozzles configured to deliver a gas to the polishing pad, the plurality of nozzles mechanically attached to the one or more brackets of the arm, each of the plurality of nozzles oriented such that an air gap is disposed between adjacent nozzles of the plurality of nozzles such that air may be pulled from the air gap and propelled with the gas towards the polishing pad.
Inventor(s): Jianxin LEI of Fremont CA (US) for applied materials, inc., Kirankumar Neelasandra SAVANDAIAH of Bangalore (IN) for applied materials, inc., Andrew MOE of Santa Clara CA (US) for applied materials, inc., Madan Kumar SHIMOGA MYLARAPPA of Bangalore (IN) for applied materials, inc.
IPC Code(s): C23C14/34
CPC Code(s): C23C14/3414
Abstract: the disclosure relates to a target for physical vapor deposition processes. in one embodiment, a physical vapor deposition (pvd) target, includes a monolithic target with a support region partially defined by a process face and radial sidewalls; and a recess within a mounting face of the monolithic target, the recess disposed opposite the process face and extending radially outward of the radial sidewalls.
Inventor(s): Charith NANAYAKKARA of Gloucester MA (US) for applied materials, inc., John HAUTALA of Beverly MA (US) for applied materials, inc.
IPC Code(s): C23C16/04, C23C16/26
CPC Code(s): C23C16/047
Abstract: a method of modifying an opening in a mask to achieve desired critical dimensions, the method including performing a pre-implant on the mask to implant the mask with a dopant material, wherein a material of the mask is densified and the opening is enlarged, directing a first radical beam at a first lateral side of the opening to deposit a layer of material on the first lateral side, and directing a second radical beam at a second lateral side of the opening opposite the first lateral side to deposit a layer of material on the second lateral side.
Inventor(s): Fredrick FISHBURN of Aptos CA (US) for applied materials, inc., Hao ZHANG of San Diego CA (US) for applied materials, inc., Zhijun CHEN of San Jose CA (US) for applied materials, inc., Johanes SWENBERG of Los Gatos CA (US) for applied materials, inc., Christopher S. OLSEN of Fremont CA (US) for applied materials, inc., Hansel LO of San Jose CA (US) for applied materials, inc., Kristopher Mikael KOSKELA of San Jose CA (US) for applied materials, inc., Hoi-Sung CHUNG of Sunnyvale CA (US) for applied materials, inc., Chang Seok KANG of San Jose CA (US) for applied materials, inc., Raghuveer Satya MAKALA of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): C23C16/455, C23C16/04, C23C16/34, C23C16/56
CPC Code(s): C23C16/45536
Abstract: a method for forming an oxide layer includes forming a protective interlayer oxide on sidewalls of a trench formed on a substrate, forming a silicon nitride layer on the protective interlayer oxide, by a plasma-enhanced atomic layer deposition (pe ald) process utilizing nitrogen-containing process gas, the silicon nitride layer having a concentration gradient of nitrogen varying from high concentration away from the protective interlayer oxide to low concentration near the protective interlayer oxide, and performing a conversion process to oxidize the formed silicon nitride layer to at least partially convert the formed silicon nitride layer to a silicon oxide layer.
Inventor(s): Ryan Sungbin HU of Santa Clara CA (US) for applied materials, inc., Kuan Chien SHEN of Sunnyvale CA (US) for applied materials, inc., Kazuyoshi KOBASHI of Santa Clara CA (US) for applied materials, inc., Chen-Yao CHAO of Santa Clara CA (US) for applied materials, inc., Masato ISHII of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): C30B25/16, H01L21/02
CPC Code(s): C30B25/165
Abstract: disclosed herein are a gas delivery module, a processing chamber, and a method for depositing a film on a substrate. in one example, a gas delivery module is provided that includes a deposition precision flow device (pfd) flow controller, a carrier pfd flow controller, and a plurality of mass flow controllers (mfcs). the deposition pfd flow controller is configured to control a flow of a deposition gas through a plurality of outlets. the carrier pfd flow controller is configured to control a flow of a carrier gas through a plurality of outlets. the first mfc of the plurality of mfcs includes a first inlet and an outlet. the first inlet of the first mfc is fluidly coupled to a first outlet of the plurality of outlets of the deposition pfd and to a first outlet of the plurality of outlets of the carrier pfd. the second mfc of the plurality of mfcs includes a second inlet and an outlet. the second inlet of the second mfc is fluidly coupled to a second outlet of the plurality of outlets of the deposition pfd and to a second outlet of the plurality of outlets of the carrier pfd. the third mfc of the plurality of mfcs includes a third inlet and an outlet. the third inlet of the third mfc is fluidly coupled to a third outlet of the plurality of outlets of the deposition pfd and to a third outlet of the plurality of outlets of the carrier pfd.
20250075795. SEAL ASSEMBLY WITH A RETAINING MECHANISM_simplified_abstract_(applied materials, inc.)
Inventor(s): Jonathan SIMMONS of San Jose CA (US) for applied materials, inc., Andreas SCHMID of Meyriez (CH) for applied materials, inc., Sahiti NALLAGONDA of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): F16J15/06, H01J37/32
CPC Code(s): F16J15/06
Abstract: disclosed herein is a seal assembly for a substrate processing chamber and a component assembly containing the seal assembly. the seal assembly includes a ring-shaped seal member; a holder disposed radially inward of the ring-shaped seal member; and a retaining mechanism coupling the ring-shaped seal member with the holder. the component assembly includes a first component coupled with a second component via a bonding layer; a groove formed by the first component, the second component, and the bonding layer; and the seal assembly disposed in the groove.
Inventor(s): Daemian Raj Benjamin Raj of Fremont CA (US) for applied materials, inc., Hassan Ali of Santa Clara CA (US) for applied materials, inc., Travis Clark Mazzy of Fremont CA (US) for applied materials, inc., Thorsten Kril of Santa Cruz CA (US) for applied materials, inc., Vignesh Kumar Venkateshwar of Sunnyvale CA (US) for applied materials, inc., Venkatanarayana Shankaramurthy of San Jose CA (US) for applied materials, inc.
IPC Code(s): G01F25/10, G05D7/06
CPC Code(s): G01F25/10
Abstract: systems and methods for monitoring and detecting a malfunction within a gas distribution system are provided. a system may first enable, by a controller, gas flow through a flow path of the gas distribution system. afterwards, the system may receive data including pressure data and/or flow rate data associated with the flow path of the gas distribution system while gas flow is enabled through the flow path. the system may process the data to determine whether the first flow path of the gas distribution system includes a malfunction. responsive to determining that the flow path includes a malfunction, the system may determine a relative location of the malfunction within the flow path, with respect to a mass flow controller (mfc) or sensor within the flow path. the system may generate a report indicating whether the flow path includes a malfunction and a relative location of any determined malfunction.
Inventor(s): Venkatakaushik VOLETI of San Jose CA (US) for applied materials, inc., Mehdi VAEZ-IRAVANI of Los Gatos CA (US) for applied materials, inc.
IPC Code(s): G01N21/88, G01N21/95, H01L21/66
CPC Code(s): G01N21/8851
Abstract: an optical inspection system for pre-bonding inspection system includes a stage on which a sample to be inspected is placed, a sensor, optical assemblies, each including an optical head having optics to direct a sample field-of-view (fov) to a portion of the sample, a first light source configured to illuminate the sample at a first oblique angle, a second light source configured to illuminate the sample at a second oblique angle, a focusing lens to focus a first optical image of the portion of the sample generated by the first light source, and a second optical image of the portion of the sample generated by the second light source onto a segment of the sensor, and a controller configured to combine the first optical image and the second optical image generated by each optical assembly, and generate a map of point defects on the sample.
Inventor(s): Venkatakaushik VOLETI of San Jose CA (US) for applied materials, inc., Yun-Ching CHANG of Pleasanton CA (US) for applied materials, inc., Dan XIE of Mountain View CA (US) for applied materials, inc., Gregory KIRK of Pleasanton CA (US) for applied materials, inc., Mehdi VAEZ-IRAVANI of Los Gatos CA (US) for applied materials, inc.
IPC Code(s): G01N21/95, G01N21/47, H01L21/66, H01L23/00
CPC Code(s): G01N21/9505
Abstract: an optical inspection system for pre-bonding inspection includes a stage having a surface on which a sample to be inspected is placed, the surface of the sample having at least parts with a two dimensional (2d) periodic pattern which may include defects, an optical head including optics, a dark-field illuminator configured to illuminate the surface of the sample at an first angle, wherein the first angle is an oblique angle, a bright-field illuminator configured to illuminate the surface at a second angle, a dark-field collection path, a bright-field collection path, and a sensor configured to detect light transmitted from the dark-field illuminator, scattered at the surface of the sample, collected by the optical head, and relayed through the dark-field collection path, and light transmitted from the bright-field illuminator, reflected at the surface of the sample, and relayed through the bright-field collection path.
Inventor(s): Davide COLLA of Treviso (IT) for applied materials, inc., Rutger MEYER TIMMERMAN THIJSSEN of San Jose CA (US) for applied materials, inc., Neal RICKS of San Jose CA (US) for applied materials, inc., Kevin MESSER of Mountain View CA (US) for applied materials, inc.
IPC Code(s): G02B5/00, F21V8/00, G02B1/00
CPC Code(s): G02B5/003
Abstract: an optical device comprising a substrate with a front surface, a back surface and a circumferential side surface is described. at least one portion of an edge of the front surface has a texturization, wherein recesses of the texturization are filled with a light-absorbent material. the circumferential side surface is free of light-absorbent material. further, a method of manufacturing a plurality of optical devices is described
20250076559. EMBEDDED FILMS FOR WAVEGUIDE COMBINERS_simplified_abstract_(applied materials, inc.)
Inventor(s): Kevin MESSER of Mountain View CA (US) for applied materials, inc., Evan WANG of Palo Alto CA (US) for applied materials, inc.
IPC Code(s): F21V8/00, G02B27/00
CPC Code(s): G02B6/0026
Abstract: a waveguide combiner including a first substrate, a second substrate, and a wavelength selective film, wherein the wavelength selective film is disposed between the first substrate and the second substrate, the wavelength selective film is operable to reflect a red light, refract and transmit a blue light, and refract and transmit a green light.
Inventor(s): Shih-Hao Kuo of Hsinchu City (TW) for applied materials, inc., Hsiu-Jen Wang of Taichung City (TW) for applied materials, inc., Ulrich Mueller of Berkeley CA (US) for applied materials, inc., Jang Fung Chen of Cupertino CA (US) for applied materials, inc.
IPC Code(s): G03F7/00, G03F7/20
CPC Code(s): G03F7/0002
Abstract: exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. the methods may include transferring the substrate to a metrology station. the methods may include measuring a topology of the substrate at the metrology station. the methods may include applying a first chucking force to the substrate to flatten the substrate. the methods may include generating a mapping of a die pattern on an exposed surface of the substrate. the methods may include transferring the substrate to a printing station. the methods may include applying a second chucking force to the substrate to flatten the substrate against a surface of the printing station. the methods may include adjusting a printing pattern based on the mapping of the die pattern. the methods may include printing the printing pattern on the exposed surface of the substrate.
Inventor(s): Ulrich Mueller of Berkley CA (US) for applied materials, inc., Thomas L. Laidig of Richmond CA (US) for applied materials, inc., Rudolf C. Brunner of Menlo Park CA (US) for applied materials, inc.
IPC Code(s): G03F7/20
CPC Code(s): G03F7/2051
Abstract: a digital lithography system includes a stage configured to support a substrate, a bridge disposed above the stage, and a first lithographic processing unit coupled to the bridge. the first lithographic processing unit coupled to the bridge can include a scanning unit, a lithographic exposure unit, and an optical system shared by the scanning unit and the lithographic exposure unit. the scanning unit is to use the optical system to generate measurements of the substrate during a measurement operation, and the lithographic exposure unit is to use the optical system to perform digital lithographic exposure of the substrate using the optical system during an exposure operation.
Inventor(s): Zhongchuan Zhang of Fremont CA (US) for applied materials, inc., Rendong Lin of San Jose CA (US) for applied materials, inc., Meenaradchagan Vishnu of San Jose CA (US) for applied materials, inc., Tamer Coskun of San Jose CA (US) for applied materials, inc., Ulrich Mueller of Berkley CA (US) for applied materials, inc., Thomas L. Laidig of Richmond CA (US) for applied materials, inc., Jang Fung Chen of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): G03F7/20, G03F9/00
CPC Code(s): G03F7/2051
Abstract: embodiments of the disclosure relate to digital lithography system and related methods, the system including at least one light source configured to emit a light beam onto a substrate via a lens, at least one image sensor, configured to detect a reflected light beam from the substrate via the lens, at least one motor configured to move the lens to focus the light beam onto the substrate, and a controller in communication with the at least one light source, the at least one image sensor and the at least one motor, wherein the controller is to actuate the at least one motor to move the lens in response to at least one signal from the at least one image sensor.
Inventor(s): Jinxin FU of Fremont CA (US) for applied materials, inc., Sihui HE of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): G06T19/00, G02B6/10
CPC Code(s): G06T19/006
Abstract: embodiments of the present disclosure generally relate to augmented reality (ar) systems. more specifically, embodiments described herein provide for an ar projection system and ar devices having the projection system. in one or more embodiments, an augmented reality device includes a projection system. the projection system includes a light engine. the light engine includes a pixel. the pixel includes an emission surface. a microlens is coupled to the emission surface of the pixel. the projection system further includes a projection lens configured to refract a first light emitted by the pixel. the first light has a first pupil length defined by a distance between a first end and a second end of the first light. the augmented reality device further includes a waveguide including an input coupler configured to incouple the first light at a first bounce length that is equivalent to the first pupil length.
20250079113. Ion Source Containing a Sputter Target_simplified_abstract_(applied materials, inc.)
Inventor(s): Graham Wright of Newburyport MA (US) for applied materials, inc.
IPC Code(s): H01J37/08, H01J37/317
CPC Code(s): H01J37/08
Abstract: an ion source with a sputter target located at the end of the ion source is disclosed. the ion source may include an indirectly heated cathode and the sputter target may be disposed on the end opposite the cathode. the ion source may contain one or more side electrodes, wherein at least one of these electrodes is electrically biased relative to the arc chamber. in one embodiment, the second end of the ion source is made of a dopant containing material and serves as the sputter target. in another embodiment, there is an opening in the second end, and an insert is disposed in this opening. the insert is made of a dopant containing material and serves as the sputter target.
20250079114. ION PROBE WITH COUPLING TO PLASMA_simplified_abstract_(applied materials, inc.)
Inventor(s): ANDREI KHOMENKO of Sunnyvale CA (US) for applied materials, inc., LEONID DORF of San Jose CA (US) for applied materials, inc., EVGENY KAMENETSKIY of San Jose CA (US) for applied materials, inc., VIACHESLAV PLOTNIKOV of San Jose CA (US) for applied materials, inc., RAJINDER DHINDSA of Pleasanton CA (US) for applied materials, inc.
IPC Code(s): H01J37/08, H01J37/32
CPC Code(s): H01J37/08
Abstract: embodiments include a plasma processing apparatus including a chamber with an inner chamber wall. a workpiece support is within the inner chamber wall, the workpiece support for supporting a workpiece in a processing region of the chamber. an ion probe extends through the chamber and inner chamber wall and into a plasma region above the workpiece.
20250079116. In-Vacuum Rotatable RF Component_simplified_abstract_(applied materials, inc.)
Inventor(s): Michael Mason Carrell of Leander TX (US) for applied materials, inc., Aaron P. Webb of Austin TX (US) for applied materials, inc., Jason M. Schaller of Austin TX (US) for applied materials, inc., William H. Park, JR. of Marblehead MA (US) for applied materials, inc., David Blahnik of Round Rock TX (US) for applied materials, inc., Wai-Ming Tam of Georgetown MA (US) for applied materials, inc.
IPC Code(s): H01J37/20, C23C14/48, H01J37/317
CPC Code(s): H01J37/20
Abstract: an apparatus that may be used to allow the rotation of a component that passes through a wall of a vacuum chamber is disclosed. the apparatus includes a rotatable shaft through which the component passes. the rotatable shaft is held in place using a holder, which retains a portion of the rotatable shaft. in some embodiments, the holder is affixed to a plate, which is then affixed to the chamber wall. the plate has an opening which is aligned to the opening in the chamber wall. a portion of the rotatable shaft passes through the opening in the plate and vacuum seals are disposed between the rotatable shaft and the plate. this apparatus may be used to allow use of rotatable components in an ion implanter.
Inventor(s): DAVID COUMOU of Webster NY (US) for applied materials, inc.
IPC Code(s): H01J37/32, G01R19/00, H03H7/40
CPC Code(s): H01J37/32183
Abstract: embodiments disclosed herein include a processing tool. in an embodiment, the processing tool comprises a power supply, an impedance matching network coupled to the power supply, a cathode, wherein the power supply is configured to supply power through the impedance matching network to the cathode, and a processing module, wherein the processing module is communicatively coupled to the power supply and the impedance matching network.
20250079137. PASSIVE LIFT PIN ASSEMBLY_simplified_abstract_(applied materials, inc.)
Inventor(s): Thomas BREZOCZKY of Los Gatos CA (US) for applied materials, inc., Kirankumar Neelasandra SAVANDAIAH of Bangalore (IN) for applied materials, inc., Srinivasan MANIVANNAN of Tamilnadu (IN) for applied materials, inc., Arun RENGARAJ of Nexus @ One-North (SG) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32715
Abstract: a substrate support assembly includes a substrate support that is moveable between a raised position, a lowered position below the raised position, and an intermediate position between the raised and lowered positions. a lift pin is disposed in a hole through the substrate support, and is movable vertically with respect to the substrate support. in use, the substrate support assembly transitions between first and second configurations. in the first configuration, the substrate support and the lift pin are coupled such that the lift pin and the substrate support move simultaneously while the substrate support moves between the lowered position and the intermediate position. in the second configuration, the substrate support and the lift pin are decoupled such that the lift pin remains stationary while the substrate support moves between the intermediate position and the raised position.
Inventor(s): Yi ZHENG of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/324, H01L21/02, H01L29/16
CPC Code(s): H01L21/324
Abstract: a method for thermally processing an optically nonopaque substrate using radiant energy. in some embodiments, the method includes flipping the optically nonopaque substrate to expose a non-structure side, depositing an opaque thermal layer on the non-structure side of the optically nonopaque substrate where the opaque thermal layer has a uniform thickness, flipping the optically nonopaque substrate to expose the structure side, and thermally processing the optically nonopaque substrate in excess of approximately 900 degrees celsius. in some embodiments, the opaque thermal layer is comprised of amorphous carbon, multiple layers of amorphous carbon with adjacent layers of the multiple layers having different optical properties, or alternating layers of different materials where a first layer of the alternating layers is comprised of amorphous carbon material and where a second layer of the alternating layers is comprised of amorphous silicon (si)-based material.
20250079192. Modular Fluid Delivery Assembly_simplified_abstract_(applied materials, inc.)
Inventor(s): Ricardo MARTINEZ of Manteca CA (US) for applied materials, inc., Jagan RANGARAJAN of San Jose CA (US) for applied materials, inc., Sami MUSTAFA of Santa Clara CA (US) for applied materials, inc., Tarun Kumar ABICHANDANI of Sunnyvale CA (US) for applied materials, inc., Lukas SYKORA of Tigard OR (US) for applied materials, inc., Shih-Yu LIU of Santa Clara CA (US) for applied materials, inc., Hung X. HOANG of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, F16K27/02
CPC Code(s): H01L21/67017
Abstract: a fluid assembly includes a base and at least one first device. the base includes a single-piece body including a base outlet, a base inlet, and a first interface including a first interface inlet and a first interface outlet. the base also includes a first flow path segment formed within the single-piece body that extends from the base inlet to the first interface outlet. the base also includes a second flow path segment formed within the single-piece body that extends from first interface inlet. the base also includes a ground path disposed within the single-piece body. the first device is attachable to the first interface to fluidly connect a first device inlet to the first interface outlet and a second device outlet to the second interface inlet.
Inventor(s): Shiyu YUE of Santa Clara CA (US) for applied materials, inc., Sahil Jaykumar PATEL of Sunnyvale CA (US) for applied materials, inc., Yu LEI of Belmont CA (US) for applied materials, inc., Wei LEI of Santa Clara CA (US) for applied materials, inc., Chih-Hsun HSU of Santa Clara CA (US) for applied materials, inc., Yi XU of San Jose CA (US) for applied materials, inc., Abulaiti HAIRISHA of Santa Clara CA (US) for applied materials, inc., Cong TRINH of Santa Clara CA (US) for applied materials, inc., Yixiong YANG of San Jose CA (US) for applied materials, inc., Ju Hyun OH of San Jose CA (US) for applied materials, inc., Aixi ZHANG of Santa Clara CA (US) for applied materials, inc., Xingyao GAO of San Jose CA (US) for applied materials, inc., Rongjun WANG of Dublin CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01J37/32, H01L21/3213
CPC Code(s): H01L21/67069
Abstract: a method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.
Inventor(s): Zhepeng CONG of San Jose CA (US) for applied materials, inc., Nyi Oo MYO of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, C23C16/458, H01L21/687
CPC Code(s): H01L21/67115
Abstract: embodiments of the present disclosure generally relate to a susceptor for thermal processing of semiconductor substrates. in one embodiment, the susceptor includes an inner region having a pattern formed in a top surface thereof, the pattern including a plurality of substrate support features separated by a plurality of venting channels. the susceptor includes a rim surrounding and coupled to the inner region, wherein the inner region is recessed relative to the rim to form a recessed pocket configured to receive a substrate. the susceptor includes a plurality of bumps extending radially inward from an inner diameter of the rim, the plurality of bumps configured to contact an outer edge of a substrate supported by the plurality of substrate support features for positioning the substrate within the recessed pocket.
Inventor(s): Punyabrahma Panda of Bangalore (IN) for applied materials, inc., Tao Zhang of San Ramon CA (US) for applied materials, inc., Ganapathy Saravanavel of Madurai (IN) for applied materials, inc., Zhi Wang of Redwood City CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, C23C16/52, G01H1/00, H04Q9/00
CPC Code(s): H01L21/67242
Abstract: an electronic device manufacturing system is provided that includes a monitoring system coupled to a tool. the monitoring system comprises a body to mount to a surface of a tool; a vibration detecting sensor disposed in or on the body, the vibration detecting sensor to generate a signal based on a vibration of the surface; a wired communication device disposed in or on the body, wherein in a first configuration the wired communication device is to transmit the signal generated by the vibration detecting sensor to the computer system via a wired connection with the computer system; and a wireless communication device disposed in or on the body, wherein in a second configuration the wireless communication device is to establish a wireless connection with the computer system and to transmit the signal generated by the vibration detecting sensor to the computer system via the wireless connection.
Inventor(s): Nithiyanantham Balasubramaniam of Leander TX (US) for applied materials, inc., Nobuyuki Kashiwagi of Cupertino CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/677
CPC Code(s): H01L21/67265
Abstract: a system includes a memory and a processing device, operatively coupled to the memory, to perform operations including receiving a signal from a reader of a contactless communication system integrated within a load port of an electronic device processing system, determining, based on the signal, whether a substrate carrier of the electronic device processing system is detected on the load port, wherein each substrate carrier of the electronic device processing system is associated with a respective tag of the contactless communication system, and in response to determining that a substrate carrier of the electronic device processing system is detected on the load port, preventing another substrate carrier from being placed on the load port.
Inventor(s): Jiang LU of Milpitas CA (US) for applied materials, inc., Shumao ZHANG of San Jose CA (US) for applied materials, inc., Liqi WU of San Jose CA (US) for applied materials, inc., Yiyang WAN of Sunnyvale CA (US) for applied materials, inc., Weifeng YE of San Jose CA (US) for applied materials, inc., Jianqiu GUO of San Jose CA (US) for applied materials, inc., Dong WANG of Santa Clara CA (US) for applied materials, inc., Qihao ZHU of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, H01L21/3205
CPC Code(s): H01L21/76879
Abstract: embodiments of the disclosure include a method of forming a gate-all-around (gaa) contact structure on a semiconductor substrate. the method will include removing material from surfaces of a feature formed in a surface of a substrate that includes a plurality of features that each include a plurality of source/drain contact surfaces, selectively forming a reaction product material over a surface of each of the plurality of source/drain contact surfaces, heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts, selectively forming a first metal layer on the surface of each of the plurality of contacts, selectively forming a second metal layer on the first metal layer, and filling the feature with a conductor material, wherein the conductor material comprises tungsten (w) or molybdenum (mo).
Inventor(s): Tyler Sherwood of Fonda NY (US) for applied materials, inc., Raghav Sreenivasan of Fremont CA (US) for applied materials, inc., Kun Li of Delmar NY (US) for applied materials, inc.
IPC Code(s): H01L23/532, H01L21/768, H01L23/00
CPC Code(s): H01L23/53238
Abstract: a structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. for example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. a semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. a dielectric film-oxide-metal-substrate structure can be formed with the dielectric film on the top surface of the stack. a multi-material etch can be used etch features in the dielectric film and the oxide in a dielectric film-oxide-metal-substrate stack. a chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.
Inventor(s): Shailesh Mishra of Bangalore (IN) for applied materials, inc., Meghna Maheshkumar Patel of Navsari (IN) for applied materials, inc.
IPC Code(s): H01L23/00, G06F21/60, G06F21/72, G06F21/73, H01L25/065
CPC Code(s): H01L23/576
Abstract: a chiplet-based system may include a first chiplet mounted to an interposer that is designated as being from one or more trusted sources, a second chiplet mounted to the interposer that is designated as not being from the one or more trusted sources, and an artificial intelligence (ai) accelerator. the ai accelerator may be programmed to monitor a state of the first chiplet, where the state may indicate an anomaly associated with the second chiplet. the ai accelerator may then select an action from a plurality of actions based at least in part on the state of the first chiplet, cause the action to be performed by the chiplet-based system, and execute a reinforcement learning algorithm update the plurality of actions based on a result of the action being performed.
Inventor(s): Tyler Sherwood of Fonda NY (US) for applied materials, inc., Raghav Sreenivasan of Fremont CA (US) for applied materials, inc.
IPC Code(s): H01L23/00, H01L21/02, H01L21/67
CPC Code(s): H01L24/05
Abstract: a structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface can be used to form devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. the dielectric constant of the dielectric film can be about or greater than 8. a device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. a technique for forming the structure can include selectively depositing the dielectric film via atomic layer deposition after features filled with metal in a top layer of oxide in an oxide-metal-substrate stack. in order to selectively deposit the dielectric film, the metal may be covered with a polymer which can be burned off. a chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.
Inventor(s): Tyler Sherwood of Fonda NY (US) for applied materials, inc., Raghav Sreenivasan of Fremont CA (US) for applied materials, inc., Maria Gorchichko of Santa Clara CA (US) for applied materials, inc., Kun Li of Delmar NY (US) for applied materials, inc.
IPC Code(s): H01L23/00, H01L21/02, H01L21/67
CPC Code(s): H01L24/05
Abstract: a first structure for semiconductor devices having a dielectric film on the top surface can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. the top surface of the dielectric film of the first structure can be hybrid bonded to a dielectric layer of a second structure. the dielectric film of the first structure and the dielectric layer of the second structure can be different dielectrics. in this way, the hybrid bonding of the two structures includes the hybrid bonding of asymmetric dielectrics.
20250081432. GATE ALL AROUND 4F2 DRAM_simplified_abstract_(applied materials, inc.)
Inventor(s): Zhijun CHEN of San Jose CA (US) for applied materials, inc., Fredrick FISHBURN of Aptos CA (US) for applied materials, inc., Tong LIU of Folsom CA (US) for applied materials, inc., Sony VARGHESE of Manchester MA (US) for applied materials, inc., Balasubramanian PRANATHARTHIHARAN of San Jose CA (US) for applied materials, inc.
IPC Code(s): H10B12/00, H01L21/762, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10B12/315
Abstract: vertical cell dynamic random-access memory (dram) arrays and methods of forming arrays with improved stability and word line resistivity are provided. the arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. the arrays include a plurality of channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels. in addition, arrays include a bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction. arrays include a gate formed around at least a portion of the plurality of channels and the bridge.
Inventor(s): Nicolas Louis BREIL of San Jose CA (US) for applied materials, inc., Avgerinos V. GELATOS of Scotts Valley CA (US) for applied materials, inc.
IPC Code(s): H01L29/40, H01L21/768, H01L29/49
CPC Code(s): H10D64/01
Abstract: a method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structure having a p-type semiconductor region for a p-type metal oxide semiconductor (p-mos) device, the cavity shaping process comprising forming a first cavity in an exposed surface of the p-type semiconductor region, performing a first selective deposition process to form a first cavity contact, selectively in the first cavity, and performing a metal treatment process on the formed first cavity contact, to remove oxides at interfaces of the first cavity contact with the first cavity.
Inventor(s): Qintao Zhang of Mt Kisco NY (US) for applied materials, inc., Samphy Hong of Saratoga Springs NY (US) for applied materials, inc.
IPC Code(s): H01L29/423, H01L29/16, H01L29/40
CPC Code(s): H10D64/513
Abstract: devices and methods may include providing a device structure having a shielding layer formed beneath each trench in a mosfet to protect trench corner breakdown. the method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. the method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.
Inventor(s): Jae Young LEE of Bedford MA (US) for applied materials, inc., Johannes M. VAN MEER of Middleton MA (US) for applied materials, inc., Yan ZHANG of Westford MA (US) for applied materials, inc., Naushad K. VARIAM of Marblehead MA (US) for applied materials, inc.
IPC Code(s): H01L21/8238, H01L29/417
CPC Code(s): H10D84/038
Abstract: disclosed herein are methods for direct backside contact formation. in some embodiments, a method may include providing a stack of layers defining a front side and a backside, wherein the front side comprises one or more devices, and forming a plurality of vias in the backside, wherein each via of the plurality of vias extends to a source/drain. the method may further include performing a dopant implant to the backside including into the plurality of vias, wherein the dopant implant is performed at a temperature greater than 300� c., forming a silicide region within each of the source/drains, and forming a backside contact within each of the plurality of vias, wherein the backside contact is formed over the silicide region.
Applied Materials, Inc. patent applications on March 6th, 2025
- Applied Materials, Inc.
- B23K26/352
- B23K26/082
- B23K26/40
- CPC B23K26/3568
- Applied materials, inc.
- B24B53/017
- H01L21/306
- CPC B24B53/017
- C23C14/34
- CPC C23C14/3414
- C23C16/04
- C23C16/26
- CPC C23C16/047
- C23C16/455
- C23C16/34
- C23C16/56
- CPC C23C16/45536
- C30B25/16
- H01L21/02
- CPC C30B25/165
- F16J15/06
- H01J37/32
- CPC F16J15/06
- G01F25/10
- G05D7/06
- CPC G01F25/10
- G01N21/88
- G01N21/95
- H01L21/66
- CPC G01N21/8851
- G01N21/47
- H01L23/00
- CPC G01N21/9505
- G02B5/00
- F21V8/00
- G02B1/00
- CPC G02B5/003
- G02B27/00
- CPC G02B6/0026
- G03F7/00
- G03F7/20
- CPC G03F7/0002
- CPC G03F7/2051
- G03F9/00
- G06T19/00
- G02B6/10
- CPC G06T19/006
- H01J37/08
- H01J37/317
- CPC H01J37/08
- H01J37/20
- C23C14/48
- CPC H01J37/20
- G01R19/00
- H03H7/40
- CPC H01J37/32183
- CPC H01J37/32715
- H01L21/324
- H01L29/16
- CPC H01L21/324
- H01L21/67
- F16K27/02
- CPC H01L21/67017
- H01L21/3213
- CPC H01L21/67069
- C23C16/458
- H01L21/687
- CPC H01L21/67115
- C23C16/52
- G01H1/00
- H04Q9/00
- CPC H01L21/67242
- H01L21/677
- CPC H01L21/67265
- H01L21/768
- H01L21/3205
- CPC H01L21/76879
- H01L23/532
- CPC H01L23/53238
- G06F21/60
- G06F21/72
- G06F21/73
- H01L25/065
- CPC H01L23/576
- CPC H01L24/05
- H10B12/00
- H01L21/762
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H10B12/315
- H01L29/40
- H01L29/49
- CPC H10D64/01
- CPC H10D64/513
- H01L21/8238
- H01L29/417
- CPC H10D84/038