Applied Materials, Inc. patent applications on March 13th, 2025
Patent Applications by Applied Materials, Inc. on March 13th, 2025
Applied Materials, Inc.: 25 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01J37/32 (5), H01L21/67 (4), G05B19/418 (3), B25J9/16 (2), H01L29/423 (2) C23C14/541 (2), H01L21/67115 (2), G06F30/27 (2), B25J9/163 (1), H01L21/0217 (1)
With keywords such as: chamber, substrate, data, device, process, processing, layer, twin, support, and further in patent application abstracts.
Patent Applications by Applied Materials, Inc.
Inventor(s): Damon K. Cox of Jarrell TX (US) for applied materials, inc., Ali Utku Pehlivan of Austin TX (US) for applied materials, inc., Paul Benjamin Reuter of Austin TX (US) for applied materials, inc.
IPC Code(s): B25J9/16, H01L21/683
CPC Code(s): B25J9/163
Abstract: a method includes causing an upper process kit ring to be removed from a lower process kit ring. the method further includes, responsive to causing the upper process kit ring to be removed from the lower process kit ring, causing, based on sensor data, a first position correction associated with the lower process kit ring. the method further includes, responsive to the first position correction, causing the upper process kit ring to be disposed on the lower process kit ring.
Inventor(s): Saitanay Naribole of Telangana (IN) for applied materials, inc., Venkata Raghavaiah Chowdhary Kode of Pflugerville TX (US) for applied materials, inc., Jagadeesh Kilaru of Karnataka (IN) for applied materials, inc., Chandrakant M. Sapkale of Bangalore (IN) for applied materials, inc., Michael Carl Hankes of Austin TX (US) for applied materials, inc.
IPC Code(s): B25J9/16, B25J13/08, B25J19/00
CPC Code(s): B25J9/1633
Abstract: a substrate gripping system includes a plunger body actuatable by an actuator and a gripper at a distal end of the plunger body. the gripper is configured to grip a substrate responsive to actuation of the plunger body by the actuator. the system further includes a sensor configured to measure a value of a parameter associated with actuation of the plunger body and a controller configured to cause the actuator to actuate the plunger body based at least partially on the value of the parameter measured by the sensor.
Inventor(s): Arvinder ManmohanSingh Chadha of San Jose CA (US) for applied materials, inc.
IPC Code(s): C23C14/54, F28F27/00
CPC Code(s): C23C14/541
Abstract: a method includes: identifying property data associated with a substrate support system; identifying target performance data associated with the substrate support system; and causing, based on the property data and the target performance data, heat transfer management of the substrate support system.
Inventor(s): Arvinder ManmohanSingh Chadha of San Jose CA (US) for applied materials, inc.
IPC Code(s): C23C14/54, F28F27/00
CPC Code(s): C23C14/541
Abstract: a method includes: identifying property data associated with a substrate support system; identifying target performance data associated with the substrate support system; determining, based on the property data and the target performance data, zone configuration data associated with the substrate support system; and causing the substrate support system to be configured based on the zone configuration data.
20250085056. PROCESS CHAMBER SUBSTRATE TRANSFER_simplified_abstract_(applied materials, inc.)
Inventor(s): Wolfgang R. ADERHOLD of Cupertino CA (US) for applied materials, inc., Peter DEMONTE of Millbrae CA (US) for applied materials, inc.
IPC Code(s): F27D3/00
CPC Code(s): F27D3/0084
Abstract: a processing system is provided including a first chamber and a second chamber. the first chamber includes: a chamber body enclosing an interior volume; an edge ring having a top and a bottom, the edge ring including a first ledge extending inwardly from the top and a second ledge extending inwardly relative to the first ledge. the first ledge is configured to support a substrate and the second ledge is configured to support a susceptor. the first chamber further includes a plurality of heating lamps positioned over the edge ring. the second chamber includes: a chamber body enclosing an interior volume; a first cooling plate; one or more robots in the interior volume of the second chamber, the one or more robots having one or more end effectors positioned over the first cooling plate; and a plurality of lift pins extending through the first cooling plate.
Inventor(s): Davide COLLA of Treviso (IT) for applied materials, inc.
IPC Code(s): G02B6/42, G02B6/24, G02B6/34
CPC Code(s): G02B6/4259
Abstract: a method for handling an optical device is provided. the method includes providing the optical device in a suspended state using a contactless suspension system, the optical device having two major surfaces. the method includes gripping the optical device in the suspended state using a gripper having a set of side supports, wherein the gripping of the optical device includes moving the set of side supports from an open position to a closed position, wherein, in the closed position, one or more side surfaces of the optical device extending between the two major surfaces of the optical device are held by the set of side supports. the method includes transporting the optical device using the gripper.
Inventor(s): Kunal SHASTRI of Santa Clara CA (US) for applied materials, inc., Sheng YUAN of Santa Clara CA (US) for applied materials, inc., Paul GALLAGHER of Santa Clara CA (US) for applied materials, inc., Gauthier BRIERE of Hoofddorp (NL) for applied materials, inc., Samarth BHARGAVA of Saratoga CA (US) for applied materials, inc., Robert Jan VISSER of Menlo Park CA (US) for applied materials, inc.
IPC Code(s): G02B27/01, B82Y20/00, G02B27/10
CPC Code(s): G02B27/0172
Abstract: implementations of the present disclosure relate to apparatus, systems, and methods of a compact, high numerical aperture light engine, for example thin optics-based light engine systems using meta-surfaces for wearable displays. one implementation includes an optical device. the optical device includes one or more spatial light modulators, wherein each spatial light modulator is an array of pixels that are individually controllable to output visible light. the optical device also includes a surface defining an exit pupil that is arranged to allow the output visible light to exit the optical device via the exit pupil. the optical device also includes one or more metasurfaces disposed between the one or more spatial light modulators and the exit pupil. the one or more metasurfaces are to focus the visible light that is output by the one or more spatial light modulators.
Inventor(s): Adolph Miller ALLEN of Oakland CA (US) for applied materials, inc., Karthik RAMANATHAN of Bangalore (IN) for applied materials, inc., Girish VENKATACHALAPATHY of Alzenau (IN) for applied materials, inc., Umesh M. KELKAR of Santa Clara CA (US) for applied materials, inc., Kasturi Tulashidas SARANG of San Jose CA (US) for applied materials, inc., Yimeng LYU of Mountain View CA (US) for applied materials, inc., Weize HU of Sunnyvale CA (US) for applied materials, inc., Ying TENG of Pacheco CA (US) for applied materials, inc., Sejune CHEON of Seoul (KR) for applied materials, inc., Shiqi DONG of Milpitas CA (US) for applied materials, inc., Paul Gerard KIELY of Santa Cruz CA (US) for applied materials, inc., Milan PRAKASH of Bangalore (IN) for applied materials, inc.
IPC Code(s): G05B19/418, H01L21/67
CPC Code(s): G05B19/41885
Abstract: a method, apparatus, and system for controlling a physical twin chamber configured to process substrates are described herein. in some embodiments, a method comprises determining, by a digital twin device, characteristics of a physical twin chamber and generating control inputs for controlling the physical twin chamber. the digital twin device comprises one or more computational models for determining the characteristics of the physical twin and for generating the control inputs. the digital twin device determines a first data set associated with the physical twin chamber. the first data set comprises process data collected by sensors configured to measure attributes of the physical twin chamber. based on the first data, the digital twin device automatically generates a second data set based on the generated control inputs and transmits the second data set to the physical twin chamber for controlling the process performed on the substrates by the physical twin chamber.
Inventor(s): Ala Moradian of San Jose CA (US) for applied materials, inc., Umesh Kelkar of Cupertino CA (US) for applied materials, inc., Prashanth Kothnur of San Jose CA (US) for applied materials, inc., Karthik Ramanathan of Bangalore (IN) for applied materials, inc., Preetham Rao of Morgan Hill CA (US) for applied materials, inc., Mudit Pasagadagula of Saratoga CA (US) for applied materials, inc., Anup Kumar D. Doddamane of Davangere (IN) for applied materials, inc.
IPC Code(s): G06F30/17
CPC Code(s): G06F30/17
Abstract: a method includes receiving, via a graphical user interface (gui), by a processing device, a first user input to view data associated with a first process chamber in a first chamber data mode. data of the first chamber data mode includes data of a process operation performed in the first process chamber. the method further includes providing, for display on the gui, first display data of the first data chamber mode responsive to receiving the first user input. the method further includes receiving a second user input to view data associated with the first process chamber in a second chamber data mode. data of the second chamber data mode includes data of a virtual process operation performed by a virtual representation of the first process chamber. the method further includes providing, for display on the gui, second display data of the second data chamber mode.
Inventor(s): Adolph Miller ALLEN of Oakland CA (US) for applied materials, inc., Karthik RAMANATHAN of Bangalore (IN) for applied materials, inc., Girish VENKATACHALAPATHY of Alzenau (IN) for applied materials, inc., Umesh M. KELKAR of Santa Clara CA (US) for applied materials, inc., Kasturi Tulashidas SARANG of San Jose CA (US) for applied materials, inc., Yimeng LYU of Mountain View CA (US) for applied materials, inc., Weize HU of Sunnyvale CA (US) for applied materials, inc., Ying TENG of Pacheco CA (US) for applied materials, inc., Sejune CHEON of Seoul (KR) for applied materials, inc., Shiqi DONG of Milpitas CA (US) for applied materials, inc., Paul Gerard KIELY of Santa Cruz CA (US) for applied materials, inc., Milan PRAKASH of Bangalore (IN) for applied materials, inc.
IPC Code(s): G06F30/27, G05B19/418
CPC Code(s): G06F30/27
Abstract: a method, apparatus, and system for controlling a multi-chamber system configured to process substrates are described herein. in some embodiments, a method comprises automatically determining, by each digital twin device a first data set associated with a corresponding process chamber of process chambers. the plurality of digital twin devices captures and models characteristics and processes of process chambers and generates control inputs for controlling the process chambers or processes executed by the chambers during the manufacturing of substrates. the method further comprises automatically generating, by each digital twin device, a second data set that comprises control inputs, and automatically transmitting the second data set to the process chamber.
Inventor(s): Adolph Miller ALLEN of Oakland CA (US) for applied materials, inc., Karthik RAMANATHAN of Bangalore (IN) for applied materials, inc., Girish VENKATACHALAPATHY of Alzenau (IN) for applied materials, inc., Umesh M. KELKAR of Santa Clara CA (US) for applied materials, inc., Kasturi Tulashidas SARANG of San Jose CA (US) for applied materials, inc., Yimeng LYU of Mountain View CA (US) for applied materials, inc., Weize HU of Sunnyvale CA (US) for applied materials, inc., Ying TENG of Pacheco CA (US) for applied materials, inc., Sejune CHEON of Seoul (KR) for applied materials, inc., Shiqi DONG of Milpitas CA (US) for applied materials, inc., Paul Gerard KIELY of Santa Cruz CA (US) for applied materials, inc., Milan PRAKASH of Bangalore (IN) for applied materials, inc.
IPC Code(s): G06F30/27, G05B19/418
CPC Code(s): G06F30/27
Abstract: a method, apparatus, and system for controlling a multi-chamber process system for substrate processing are described herein. in some embodiments, a method comprises determining, by each digital twin device, of a plurality of digital twin devices, a first data set associated with at least one process chamber of a plurality of chamber processes, and the corresponding processes for processing a plurality of substrates. each digital twin device comprises one or more computational models. the first data set comprises measurements reported by probes or sensors within the at least one chamber process, or data collected and reported by internal sensors of the digital twin device. the method further automatically generating, by each digital twin device a second data set based on, at least in part, the first data set, and by executing one or more computational models of the digital twin device.
20250087461. PULSED VOLTAGE-ASSISTED PLASMA STRIKE_simplified_abstract_(applied materials, inc.)
Inventor(s): Shreeram Jyoti DASH of San Jose CA (US) for applied materials, inc., Michael T. NICHOLS of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32146
Abstract: embodiments provided herein generally include apparatus, plasma processing systems and methods for controlling plasma initiation and maintenance. some embodiments are directed to an apparatus for processing a substrate in a plasma processing system. the apparatus generally includes: a pulsed voltage (pv) signal generator configured to provide a bias signal to a plasma load to initiate a plasma in a plasma chamber, wherein the bias signal comprises a first burst having a first duration, the first burst including a series of pulses; and a radio frequency (rf) signal generator configured to provide an rf signal to the plasma load for a second duration, wherein the first duration is less than % of the second duration, and wherein the first burst occurs at a beginning of the second duration.
Inventor(s): Yue GUO of Redwood City CA (US) for applied materials, inc., Kartik RAMASWAMY of San Jose CA (US) for applied materials, inc., A N M Wasekul AZAD of Santa Clara CA (US) for applied materials, inc., Nicolas J. BRIGHT of Arlington WA (US) for applied materials, inc., Yang YANG of San Diego CA (US) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32183
Abstract: embodiments provided herein generally include apparatus, plasma processing systems and methods for tuning in a radio frequency (rf) plasma processing system for improving substrate processing metrics. some embodiments are directed to a method for processing a substrate in a plasma processing system. the method generally includes: sensing, via one or more sensors, one or more intermodulation or harmonic components of a signal at a node coupled to a plasma chamber; and controlling one or more signal processing devices of the plasma processing system to process the substrate based on the one or more intermodulation or harmonic components and in accordance with a frequency domain configuration identified by analyzing one or more substrate processing metrics.
Inventor(s): Vijay D. Parkhe of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32724
Abstract: methods for improving thermal uniformity on a surface of a substrate support assembly. one method includes temporarily clamping a ceramic puck plate to a cooling plate of a substrate support assembly with one or more layers of bonding material between the ceramic puck and the cooling plate. the method further includes heating the ceramic puck plate to a target temperature, cooling the cooling plate to an operating temperature, and recording temperatures at a plurality of locations on a substrate support surface of the ceramic puck plate. the method further includes modifying, based on the recorded temperatures, one or more properties of the one or more layers of the bonding material to achieve a target temperature profile on the substrate support surface.
20250087471. MULTI-STAGE PUMPING LINER_simplified_abstract_(applied materials, inc.)
Inventor(s): Mingle Tong of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, C23C16/44, C23C16/455, C23C16/458, H01L21/67
CPC Code(s): H01J37/32834
Abstract: exemplary semiconductor processing systems may include a pumping system, a chamber body that defines a processing region, and a pumping liner disposed within the processing region. the pumping liner may define an annular member characterized by a wall that defines an exhaust aperture coupled to the pumping system. the annular member may be characterized by an inner wall that defines a plurality of apertures distributed circumferentially along the inner wall. a plenum may be defined in the annular member between interior surfaces of the walls. a divider may be disposed within the plenum, where the divider separates the plenum into a first plenum chamber and a second plenum chamber, wherein the first plenum chamber is fluidly accessible from the apertures defined through the inner wall, and wherein the divider defines at least one aperture providing fluid access between the first plenum chamber and the second plenum chamber.
20250087477. METHODS OF FORMING SILICON NITRIDE FILMS_simplified_abstract_(applied materials, inc.)
Inventor(s): Joseph AuBuchon of San Jose CA (US) for applied materials, inc., Kenneth S. Collins of San Jose CA (US) for applied materials, inc., Hanhong Chen of Milpitas CA (US) for applied materials, inc., Philip A. Kraus of San Jose CA (US) for applied materials, inc., Michael Rice of Pleasanton CA (US) for applied materials, inc.
IPC Code(s): H01L21/02
CPC Code(s): H01L21/0217
Abstract: methods of depositing improved quality silicon nitride (sin) films are disclosed. exemplary methods include exposing a semiconductor substrate in a semiconductor processing chamber to a silicon-containing precursor, to a first plasma produced from a first gas mixture comprising helium (he) and nitrogen (n), the first gas mixture comprising a ratio of helium:nitrogen in a range of from 20:1 to 1000:1, and exposing the semiconductor substrate to a second plasma produced from a second gas mixture comprising helium (he), nitrogen (n), and ammonia (nh).
Inventor(s): Chen-Ying WU of Santa Clara CA (US) for applied materials, inc., Yi-Chiau HUANG of Fremont CA (US) for applied materials, inc., Zhiyuan YE of San Jose CA (US) for applied materials, inc., Schubert S. CHU of San Francisco CA (US) for applied materials, inc., Errol Antonio C. SANCHEZ of Tracy CA (US) for applied materials, inc., Brian Hayes BURROWS of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, C30B25/08, C30B25/18, C30B29/06, C30B33/02, C30B33/12, C30B35/00, H01L21/3065, H01L21/324
CPC Code(s): H01L21/02636
Abstract: aspects of the present disclosure relate to apparatus, systems, and methods of using atomic hydrogen radicals with epitaxial deposition. in one aspect, nodular defects (e.g., nodules) are removed from epitaxial layers of substrate. in one implementation, a method of processing substrates includes selectively growing an epitaxial layer on one or more crystalline surfaces of a substrate. the epitaxial layer includes silicon. the method also includes etching the substrate to remove a plurality of nodules from one or more non-crystalline surfaces of the substrate. the etching includes exposing the substrate to atomic hydrogen radicals. the method also includes thermally annealing the epitaxial layer to an anneal temperature that is 600 degrees celsius or higher.
Inventor(s): Baiwei Wang of Santa Clara CA (US) for applied materials, inc., Rohan Puligoru Reddy of San Jose CA (US) for applied materials, inc., Xiaolin C. Chen of San Ramon CA (US) for applied materials, inc., Wanxing Xu of Sunnyvale CA (US) for applied materials, inc., Zhenjiang Cui of San Jose CA (US) for applied materials, inc., Anchuan Wang of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/311
CPC Code(s): H01L21/31122
Abstract: exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. a substrate may be housed within the processing region. the substrate may define an exposed region of a metal-containing hardmask material and an exposed region of a material characterized by a dielectric constant of less than or about 4.0. the methods may include contacting the substrate with the etchant precursor. the methods may include removing at least a portion of the metal-containing hardmask material.
Inventor(s): Shashank Sharma of Fremont CA (US) for applied materials, inc., Wolfgang Robert Aderhold of Cupertino CA (US) for applied materials, inc., Vikash Banthia of Los Altos CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/324, H01L21/683
CPC Code(s): H01L21/67115
Abstract: a system includes a chamber body defining a processing volume. the system further includes a substrate support pedestal positioned in the processing volume and operable to support a substrate, the substrate support pedestal including one or more channels, where a coolant medium flows through the one or more channels to facilitate heat transfer from the substrate to the coolant medium. the system further includes a coolant medium circulator to circulate the coolant medium through the one or more channels. the system further includes a substrate temperature sensor operatively coupled to the chamber body, where the substrate temperature sensor measures a temperature of the substrate. the system further includes a coolant medium circulation controller, coupled to the coolant medium circulator and the substrate temperature sensor, to control a rate at which the coolant medium is circulated through the one or more channels.
Inventor(s): Tobin KAUFMAN-OSBORN of Sunnyvale CA (US) for applied materials, inc., Christopher S. OLSEN of Fremont CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01J37/32
CPC Code(s): H01L21/67115
Abstract: the present disclosure provides an apparatus and methods for processing a substrate. the apparatus includes a chamber body defining a processing volume. the apparatus further includes a base ring and a substrate support disposed in the processing volume. a gas source assembly is in fluid communication with an inlet of the chamber body. an exhaust assembly is in fluid communication with an outlet of the chamber body. a side injection assembly is in fluid communication with a first gas source, in which the side injection assembly is coupled to the base ring of the chamber body. the side injection assembly includes an elongated structure that extends towards the processing volume and a first side inject actuator coupled to the elongated structure and configured to control a first inject angle of the elongated structure relative to the base ring
20250087524. PROCESS KIT ENCLOSURE SYSTEM_simplified_abstract_(applied materials, inc.)
Inventor(s): Helder Lee of San Jose CA (US) for applied materials, inc., Nicholas Michael Kopec of Sunnyvale CA (US) for applied materials, inc., Leon Volfovski of Foster City CA (US) for applied materials, inc., Douglas R. McAllister of San Ramon CA (US) for applied materials, inc., Andreas Schmid of Meyriez (CH) for applied materials, inc., Jeffrey Hudgens of San Francisco CA (US) for applied materials, inc., Yogananda Sarode Vishwanath of Bangalore (IN) for applied materials, inc., Steven Babayan of Los Altos CA (US) for applied materials, inc.
IPC Code(s): H01L21/687, H01L21/673, H01L21/677, H01L21/68
CPC Code(s): H01L21/68707
Abstract: a process kit enclosure system includes walls and a retention device structure. the retention device structure includes a retention device post and a retention device fin. the retention device fin in a first position is disposed above and secures a process kit ring supported in the interior volume of the process kit enclosure system. the retention device fin is rotated from the first position to be in a second position to be outside a boundary of the process kit ring. the retention device post is aligned with and inserts into a recess formed by a top cover of the process kit enclosure system responsive to the retention device post being in the first position. the retention device post is misaligned with and blocked from inserting into the recess formed by the top cover responsive to the retention device post of the retention device structure being in the second position.
Inventor(s): Tyler Sherwood of Fonda NY (US) for applied materials, inc., Raghav Sreenivasan of Fremont CA (US) for applied materials, inc., Michael Chudzik of Mountain View CA (US) for applied materials, inc., Maria Gorchichko of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L23/498, H01L21/48, H01L23/48, H01L23/64
CPC Code(s): H01L23/49838
Abstract: the interconnect resistances in a hybrid bonded structure can be controlled and designed. the resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. a first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. the techniques described herein include designing interconnects and forming interconnects with particular resistances.
Inventor(s): San-Kuei Lin of Los Gatos CA (US) for applied materials, inc., Pradeep K. Subrahmanyan of Los Gatos CA (US) for applied materials, inc.
IPC Code(s): H01L21/822, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D84/038
Abstract: embodiments of the disclosure advantageously provide semiconductor devices cfet in particular, and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers that are protected from material loss during removal of a middle sacrificial layer. the cfet described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hgaa structure on the substrate; a middle sacrificial layer on a top surface of the first hgaa structure, the middle sacrificial layer comprising silicon germanium (sige); and a second hgaa structure on a top surface of the sacrificial layer. each of the first hgaa and the second hgaa comprise alternating layers of nanosheet channel layer that comprise silicon (si) and nanosheet release layer that comprise silicon germanium (sige). the middle sacrificial layer and the nanosheet release layers can comprise silicon germanium (sige) having the same or substantially the same geranium content.
Inventor(s): San-Kuei Lin of Los Gatos CA (US) for applied materials, inc., Pradeep K. Subrahmanyan of Los Gatos CA (US) for applied materials, inc.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/10, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10D84/85
Abstract: methods of manufacturing electronic devices are described. embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (cfets) that meet reduced thickness, reduced leakage, lower thermal budget, and vrequirements (including multi-v), and have improved device performance and reliability. some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-� dielectric layer after the annealing process (in dipole last processes).
Inventor(s): Xiaodong YANG of Xi'an (CN) for applied materials, inc., Lizhong SUN of San Jose CA (US) for applied materials, inc.
IPC Code(s): H10N30/079, H10N30/00, H10N30/076, H10N30/853
CPC Code(s): H10N30/079
Abstract: a method for forming and a film stack for a piezoelectric device includes a first seed layer of aluminum nitride, aluminum oxide, or silicon nitride formed on a substrate, an intermediate film layer formed on the first seed layer at a temperature of approximately 300 degrees celsius to approximately 400 degrees celsius where the intermediate film layer includes a first layer of a first material and a second layer of a second material that is different from the first material, a second seed layer of aluminum nitride, aluminum oxide, or silicon nitride formed on the intermediate film layer, and an active film layer with a full width half maximum (fwhm) of 1.2 degrees or less formed on the second seed layer.
Applied Materials, Inc. patent applications on March 13th, 2025
- Applied Materials, Inc.
- B25J9/16
- H01L21/683
- CPC B25J9/163
- Applied materials, inc.
- B25J13/08
- B25J19/00
- CPC B25J9/1633
- C23C14/54
- F28F27/00
- CPC C23C14/541
- F27D3/00
- CPC F27D3/0084
- G02B6/42
- G02B6/24
- G02B6/34
- CPC G02B6/4259
- G02B27/01
- B82Y20/00
- G02B27/10
- CPC G02B27/0172
- G05B19/418
- H01L21/67
- CPC G05B19/41885
- G06F30/17
- CPC G06F30/17
- G06F30/27
- CPC G06F30/27
- H01J37/32
- CPC H01J37/32146
- CPC H01J37/32183
- CPC H01J37/32724
- C23C16/44
- C23C16/455
- C23C16/458
- CPC H01J37/32834
- H01L21/02
- CPC H01L21/0217
- C30B25/08
- C30B25/18
- C30B29/06
- C30B33/02
- C30B33/12
- C30B35/00
- H01L21/3065
- H01L21/324
- CPC H01L21/02636
- H01L21/311
- CPC H01L21/31122
- CPC H01L21/67115
- H01L21/687
- H01L21/673
- H01L21/677
- H01L21/68
- CPC H01L21/68707
- H01L23/498
- H01L21/48
- H01L23/48
- H01L23/64
- CPC H01L23/49838
- H01L21/822
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H10D84/038
- H01L29/10
- CPC H10D84/85
- H10N30/079
- H10N30/00
- H10N30/076
- H10N30/853
- CPC H10N30/079