Applied Materials, Inc. patent applications on January 30th, 2025
Patent Applications by Applied Materials, Inc. on January 30th, 2025
Applied Materials, Inc.: 30 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01J37/32 (7), H01L21/02 (6), C23C16/455 (5), H01L21/67 (5), C23C16/44 (4) B23Q7/1431 (1), H01L21/0217 (1), H01L29/42392 (1), H01L29/775 (1), H04N23/74 (1)
With keywords such as: substrate, processing, chamber, layer, disposed, gas, body, include, methods, and process in patent application abstracts.
Patent Applications by Applied Materials, Inc.
20250033156. SWAPPER FOR A CLUSTER TOOL_simplified_abstract_(applied materials, inc.)
Inventor(s): Upendra UMMETHALA of Santa Clara CA (US) for applied materials, inc., Praveen CHORAGUDI of Singapore (SG) for applied materials, inc., Kaushik ALAYAVALLI of Sunnyvale CA (US) for applied materials, inc., Bhawesh AGRAWAL of Bangalore (IN) for applied materials, inc.
IPC Code(s): B23Q7/14, B23Q11/14
CPC Code(s): B23Q7/1431
Abstract: a swapper assembly of a cluster tool includes a housing, at least two swappers, and a motor assembly. the at least two swappers are at least partially disposed within and rotatable relative to the housing. each swapper includes a body, a first arm, and a second arm. the first arm and second arm are rotatable relative to the body. the motor assembly includes at least one motor, and the motor assembly is configured to operate the at least two swappers simultaneously to change the position of the first arm and second arm.
Inventor(s): Xinyi LU of Santa Clara CA (US) for applied materials, inc., Srikant PATHAK of Diamond Bar CA (US) for applied materials, inc., Sudhakar MADHUSOODHANAN of Pleasanton CA (US) for applied materials, inc.
IPC Code(s): C08F20/56, B24B37/22, B24B37/24, C08L39/06
CPC Code(s): C08F20/56
Abstract: polishing pads having porogen-features, methods of manufacturing polishing pads having porogen features, and compositions for manufacturing polishing pads having porogen features, and more particularly, to polishing pads used for chemical mechanical polishing (cmp) of a substrate in electronic device processing are provided. in one aspect, the porogen-forming composition, in proportions based on a total weight of the porogen-forming composition, includes (a) from about 60 to about 80 wt. % of an acrylamide monomer compound selected from acryloylmorpholine, n, n-dimethylacrylamide, or a combination thereof. the curable porogen-forming composition further includes (b) from about 10 to about 40 wt. % of a polyhydroxy compound having two or more hydroxyl groups. the curable porogen-forming composition further includes (c) from about 0.2 wt. % to about 4 wt. % of a photoinitiator component.
Inventor(s): Mukhles SOWWAN of Sunnyvale CA (US) for applied materials, inc., Shu-Kwan LAU of Sunnyvale CA (US) for applied materials, inc., Toshiyuki NAKAGAWA of Narita-Shi (JP) for applied materials, inc.
IPC Code(s): C23C16/455, C23C16/458
CPC Code(s): C23C16/45557
Abstract: embodiments of the disclosure provided herein include an apparatus and system for semiconductor processing. the apparatus includes a processing chamber. the processing chamber includes a substrate support disposed within a processing volume, a controller coupled to the processing chamber, and a carrier and feed ring disposed around the processing volume. the carrier and feed ring includes a ring body, a radical source coupled to at least one ring gas port on a first side of the ring body, and a high-vacuum pump in fluid communication with a ring vacuum port disposed on a second side of the ring body.
20250034708. MULTI-SUBSTRATE PROCESSING SYSTEM_simplified_abstract_(applied materials, inc.)
Inventor(s): Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): C23C16/455, C23C16/44, C23C16/48, H01L21/677
CPC Code(s): C23C16/45561
Abstract: a processing tool is provided including an exhaust inlet; two or more process chambers surrounding the exhaust inlet, each process chamber including: a chamber body enclosing an interior volume, the chamber body including a plurality of sidewalls that include one or more outer walls and one or more inner walls; one or more substrate supports disposed in the interior volume; a plurality of lamps positioned over each substrate support; a window positioned between the plurality of lamps and the substrate support; and a gas inlet that is located closer to one of the one or more outer walls than the gas inlet is to each of the one or more inner walls.
Inventor(s): Chetan Ramachandra NAIK of Bengaluru (IN) for applied materials, inc., Anand KUMAR of Bengaluru (IN) for applied materials, inc.
IPC Code(s): F16K1/36, F16K1/42, F16K27/02
CPC Code(s): F16K1/36
Abstract: embodiments of symmetric flow valves for use in substrate processing chambers are provided herein. in some embodiments, a symmetric flow valve includes: a valve body having sidewalls, a bottom plate, and a top plate that together define an interior volume, wherein the top plate includes a plurality of axisymmetrically disposed openings arranged in a non-linear manner, and wherein the bottom plate includes a port opening; an actuator disposed above the top plate and coupled to a central region of the top plate radially inward of the plurality of axisymmetrically disposed openings; and a poppet disposed in the interior volume and coupled to the actuator to move the poppet vertically within the interior volume, wherein the poppet is configured to selectively seal the plurality of axisymmetrically disposed openings or the port opening.
20250035227. FLUID DELIVERY MOUNTING PANEL AND SYSTEM_simplified_abstract_(applied materials, inc.)
Inventor(s): Sohrab Zokaei of Los Altos CA (US) for applied materials, inc., Kiran Garikipati of Santa Clara CA (US) for applied materials, inc., Shawn Thanhsan Le of San Jose CA (US) for applied materials, inc.
IPC Code(s): F16K27/00, F15B13/08, F15B19/00, F16K37/00
CPC Code(s): F16K27/003
Abstract: an apparatus includes a mounting panel having a plurality of diffusion-bonded metal plates that form: a reservoir to contain a process fluid; and multiple channels through which to flow the process fluid, wherein at least a pair of the multiple channels are connected with the reservoir. a temperature sensor is attached to a top of the mounting panel and is in fluid communication with the reservoir through one of a plurality of vias formed in the mounting panel.
Inventor(s): Khokan C. PAUL of Cupertino CA (US) for applied materials, inc.
IPC Code(s): G01N21/55, C30B25/16
CPC Code(s): G01N21/55
Abstract: embodiments of the disclosure provided herein include a system and method for improved signal-to-noise ratio correction in an epitaxial chamber integrating in-situ reflectometry. the system includes a processing chamber and a susceptor assembly configured to rotate a substrate. an in-situ reflectometry (isr) system is coupled to the processing chamber and configured to receive isr signals indicating properties of a substrate on the susceptor assembly. a controller is configured to determine substrate rotation speed, determine time per substrate revolution using the substrate rotation speed, determine an isr samples acquisition per revolution using the time per substrate revolution, calculate a total samples value using an integer value and the isr samples acquisition per revolution, determine if the total samples value is a full integer, and upon determining that the total samples value is a full integer, calibrate the isr signals using the total samples value.
Inventor(s): Suketu Parikh of San Jose CA (US) for applied materials, inc., Jimmy Iskandar of Fremont CA (US) for applied materials, inc., Tsz Keung Cheung of San Jose CA (US) for applied materials, inc., Chih Wei Lin of Hsinchu City (TW) for applied materials, inc., Michael D. Armacost of San Jose CA (US) for applied materials, inc.
IPC Code(s): G01R19/12, H01L21/66
CPC Code(s): G01R19/12
Abstract: an electronic device manufacturing system configured to obtain current sensor data associated with a sensor of a substrate manufacturing system and determine a slope value associated with the current sensor data. responsive to determining that the slope value satisfied a threshold criterion associated with a fault detection limit, at least one of an alert is generated or a corrective action performed.
Inventor(s): David Coumou of Webster NY (US) for applied materials, inc., Zhi Wang of Sunnyvale CA (US) for applied materials, inc., Tao Zhang of San Ramon CA (US) for applied materials, inc., David Peterson of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32183
Abstract: embodiments disclosed herein include a process power controller for a plasma processing tool. in an embodiment, the process power controller includes a process power source optimizer, a source predictor, and a process uniformity controller. in an embodiment, the source predictor is communicatively coupled to the process power source optimizer and the process uniformity controller.
Inventor(s): Dmitry LUBOMIRSKY of Cupertino CA (US) for applied materials, inc., Junghoon KIM of Santa Clara CA (US) for applied materials, inc., Hyun Joo LEE of Santa Clara CA (US) for applied materials, inc., Pranav Vijay GADRE of Santa Clara CA (US) for applied materials, inc., Adib KHAN of Santa Clara CA (US) for applied materials, inc., Nithin Thomas ALEX of Bangalore (IN) for applied materials, inc., Douglas A. BUCHBERGER, Jr. of Livermore CA (US) for applied materials, inc., Qiwei LIANG of Fremont CA (US) for applied materials, inc., Ellie Y. YIEH of San Jose CA (US) for applied materials, inc., Shekhar ATHANI of Bangalore (IN) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32403
Abstract: disclosed herein is a processing system. the processing system has an upper chamber body and a lower chamber body defining a processing environment. an upper heater is moveably disposed in the upper chamber body. the upper heater has a moveable support and an upper step formed along an outer perimeter. a lower showerhead is fixedly disposed in the lower chamber body. the lower showerhead includes a top surface configured to support a substrate, a lower step disposed along an outer perimeter wherein the substrate is configured to extend from the top surface partially over the lower step. lift pins are disposed in the lower showerhead and configured to extend through the top surface and support the substrate thereon. gas holes are disposed in a first zone along the top surface and a second zone on the step and configured to independently flow both a process and non-process gas.
Inventor(s): Zhepeng CONG of San Jose CA (US) for applied materials, inc., Ashur J. ATANOS of San Jose CA (US) for applied materials, inc., Nimrod SMITH of Cupertino CA (US) for applied materials, inc., Khokan C. PAUL of Cupertino CA (US) for applied materials, inc., Tao SHENG of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, H01L21/67
CPC Code(s): H01J37/32449
Abstract: a flow apparatus and process chamber having the same are described herein. in one example, flow apparatus for use in semiconductor processing comprises an inject assembly and an inductive heater coupled to the inject assembly. the inject assembly comprises an inject body, a first gas inlet configured to flow a first gas through the inject body, and a plurality of flow channels disposed in the inject body, the plurality of flow channels coupled to the first gas inlet. the inductive heater is configured to heat a gas and comprises a heater housing, a graphite rod disposed in the heater housing, the graphite rod having a distal end and proximate end, an inductive coil disposed around the graphite rod, and a second gas inlet configured to flow a second gas between the heater housing and a graphite rod.
20250037976. PROCESS STACK FOR CVD PLASMA TREATMENT_simplified_abstract_(applied materials, inc.)
Inventor(s): Anirudh K. Alewoor of Bangalore (IN) for applied materials, inc., Akshay Dhanakshirur of Hubli (IN) for applied materials, inc., Mayur Govind Kulkarni of Bangalore (IN) for applied materials, inc.
IPC Code(s): H01J37/32, C23C16/44
CPC Code(s): H01J37/32458
Abstract: gas distribution assemblies, processing chambers, and methods for processing substrates are provided. a substrate processing chamber includes a chamber body having a first end and a second end, a lid coupled to the first end of the chamber body, an isolator disposed on an upper surface of the lid, a faceplate disposed on an upper surface of the isolator, a substrate support disposed on a shaft extending through the second end of the chamber body, a pumping ring positioned within the chamber body, and an exhaust outlet in fluid communication with a system foreline and the plurality of apertures. the processing chamber defines a processing region between the substrate support and the faceplate. the pumping ring includes a flange extending in a plane generally parallel with a top surface of the substrate support that defines a plurality of apertures.
Inventor(s): Sanjeev Baluja of Campbell CA (US) for applied materials, inc., Chaowei Wang of San Diego CA (US) for applied materials, inc., Kevin Griffin of Livermore CA (US) for applied materials, inc., Kenneth Brian Doering of San Jose CA (US) for applied materials, inc., Hanhong Chen of Milpitas CA (US) for applied materials, inc., Joseph AuBuchon of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, H01L21/67
CPC Code(s): H01J37/32495
Abstract: gas distribution assemblies for semiconductor devices are described. the gas distribution assemblies include a backplate, a faceplate, a counterbored hole, and at least one orifice. the at least one orifice includes, for example, at least one straight orifice, or at least two angled orifices. some embodiments of the gas distribution assemblies provide for reduced plasma damage in a processing chamber. some embodiments of the gas distribution assemblies provide for reduced jetting on a substrate in a processing chamber. methods of reducing plasma damage in gas distribution assemblies are also described.
Inventor(s): Mina T. FARAG of Cupertino CA (US) for applied materials, inc., Terry BLUCK of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32825
Abstract: methods and systems for transferring an alkali metal film, for example, a lithium film or a sodium film, from a flexible carrier substrate, for example, a polyethylene terephthalate (pet) substrate onto a metallic-containing substrate, for example, a copper foil, is provided. the methods and systems utilize atmospheric plasma in combination within a roll-to-roll process to facilitate the transfer of the alkali metal film while etching away residue from a release layer or reaction layer formed during high-temperature deposition of the lithium film. the resulting pristine lithium surface can then be passivated. the methods and systems are especially useful for applications in lithium-ion batteries and other energy storage devices.
20250037980. MULTI-PORT CROSS FLOW SYSTEM_simplified_abstract_(applied materials, inc.)
Inventor(s): Rupankar Choudhury of Agartala (IN) for applied materials, inc., Sanjay G. Kamath of Fremont CA (US) for applied materials, inc., Juan Carlos Rocha-Alvarez of San Carlos CA (US) for applied materials, inc., Sridhar Bachu of Hyderabad (IN) for applied materials, inc., Mukesh Singh Dhami of Lucknow (IN) for applied materials, inc., Dan-il Yoon of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, C23C16/44, C23C16/455
CPC Code(s): H01J37/32862
Abstract: a processing chamber and port adaptor are provided. processing chambers include a chamber body having a lid coupled to the first end of the chamber body, a gas ring adjacent the first end of the chamber body, and a substrate support, where a processing region is defined between the substrate support and the lid. the processing chamber includes a port adapter coupled to the second end of the chamber body. the port adapter includes a body defining a plurality of apertures in fluid communication with the processing region, where each of the apertures are spaced apart along the body such that a distance between adjacent apertures is within about 20% of an average aperture spacing distance, an individually controllable valve fluidly coupled to one or more of the plurality of apertures, and an exhaust system in fluid communication with a system foreline and the plurality of apertures.
Inventor(s): Stephen Weeks of Morrisville VT (US) for applied materials, inc., Hansel Lo of San Jose CA (US) for applied materials, inc., John Tolle of Gilbert AZ (US) for applied materials, inc., Christopher S. Olsen of Fremont CA (US) for applied materials, inc., Siddarth Krishnan of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02
CPC Code(s): H01L21/02164
Abstract: exemplary semiconductor processing methods may include performing a pre-treatment on a substrate housed within a processing region of a semiconductor processing chamber. the substrate may include a layer of silicon-and-carbon-containing material. the pre-treatment may remove native oxide or residue from a surface of the layer of silicon-and-carbon-containing material. the methods may include providing a silicon-containing precursor to the processing region of the semiconductor processing chamber. the methods may include contacting the substrate with the silicon-containing precursor. the contacting may deposit a layer of silicon-containing material on the layer of silicon-and-carbon-containing material. the methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. the methods may include contacting the substrate with the oxygen-containing precursor. the contacting may oxidize the layer of silicon-containing material to form a layer of silicon-and-oxygen-containing material.
20250037989. SEQUENTIAL PLASMA AND THERMAL TREATMENT_simplified_abstract_(applied materials, inc.)
Inventor(s): Ning Li of San Jose CA (US) for applied materials, inc., Shuaidi Zhang of San Jose CA (US) for applied materials, inc., Mihaela A. Balseanu of Sunnyvale CA (US) for applied materials, inc., Qi Gao of Wilmington MA (US) for applied materials, inc., Rajesh Prasad of Lexington MA (US) for applied materials, inc., Tomohiko Kitajima of San Jose CA (US) for applied materials, inc., Chang Seok Kang of Santa Clara CA (US) for applied materials, inc., Deven Matthew Raj Mittal of Middleton MA (US) for applied materials, inc., Kyu-Ha Shim of Andover MA (US) for applied materials, inc.
IPC Code(s): H01L21/02, C23C16/34, C23C16/56, H10B41/27, H10B41/35, H10B43/27, H10B43/35
CPC Code(s): H01L21/0217
Abstract: methods of manufacturing memory devices are provided. the methods improve the quality of a selectively deposited silicon-containing dielectric layer. the method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. the selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800� c. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.
Inventor(s): Qinghua Zhao of Sunnyvale CA (US) for applied materials, inc., Rui Cheng of San Jose CA (US) for applied materials, inc., Ruiyun Huang of Santa Clara CA (US) for applied materials, inc., Dong Hyung Lee of Danville CA (US) for applied materials, inc., Aykut Aydin of Sunnyvale CA (US) for applied materials, inc., Karthik Janakiraman of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/3205
CPC Code(s): H01L21/0234
Abstract: exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. a substrate may be disposed within the processing region of the semiconductor processing chamber. the methods may include depositing a silicon-containing material on the substrate. the silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the silicon-containing material within at least one of the one or more recessed features along the substrate. the methods may also include treating the silicon-containing material with a hydrogen-containing gas, such as plasma effluents of the hydrogen-containing gas, which may cause a size of the seam or void to be reduced.
Inventor(s): Ruiying HAO of San Jose CA (US) for applied materials, inc., Thomas John KIRSCHENHEITER of New York NY (US) for applied materials, inc., Fredrick FISHBURN of Los Gatos CA (US) for applied materials, inc., Abhishek DUBE of Fremont CA (US) for applied materials, inc., Raghuveer S. MAKALA of Campbell CA (US) for applied materials, inc., Balasubramanian PRANATHARTHIHARAN of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/306
CPC Code(s): H01L21/02532
Abstract: a semiconductor device and a method for manufacturing thereof. a substrate is provided. one or more groups of layers are formed on top of the substrate. a compensation layer is formed on top of at least one group of layers. at least one silicon layer is formed on top of the compensation layer. at least a portion of one or more layers in the one or more groups of layers is etched. the semiconductor device is formed.
20250038000. SiC TRENCH BOTTOM CORNER ROUNDING_simplified_abstract_(applied materials, inc.)
Inventor(s): Qintao ZHANG of Mt Kisco NY (US) for applied materials, inc., Ludovico MEGALINI of Mountain View CA (US) for applied materials, inc., Wei ZOU of Lexington MA (US) for applied materials, inc., Hans-Joachim L. GOSSMANN of Summit NJ (US) for applied materials, inc., William O. CHARLES of Winchester MA (US) for applied materials, inc.
IPC Code(s): H01L21/04, H01L21/266, H01L21/306, H01L29/40
CPC Code(s): H01L21/0475
Abstract: disclosed herein are methods for forming mosfet trenches with improved corner properties. in some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. the method may further include implanting the device structure by delivering ions into the corner and into the bottom of the trench, and etching the trench to increase rounding of the corner.
Inventor(s): Upendra UMMETHALA of Santa Clara CA (US) for applied materials, inc., Tuan Anh NGUYEN of San Jose CA (US) for applied materials, inc., Kaushik ALAYAVALLI of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/677, H01L21/687
CPC Code(s): H01L21/67259
Abstract: a cluster tool includes: a factory interface including a first robot with an end effector; a first processing mainframe coupled to the factory interface, including: a first processing chamber; a first load lock including a first opening facing the factory interface configured to receive the end effector of the first robot, the first load lock further including a first slit valve configured to selectively open and close the first opening; at least one first lcf sensor disposed between the factory interface and the first slit valve; and a swapper assembly disposed between the first load lock and the first processing chamber, wherein the swapper assembly includes a first swapper configured to swap substrates between the first processing chamber and the first load lock along a first trajectory.
Inventor(s): Douglas Brian Baumgarten of Round Rock TX (US) for applied materials, inc., Russell Kaplan of Sunnyvale CA (US) for applied materials, inc., Amitabh Puri of San Jose CA (US) for applied materials, inc., Paul B. Reuter of Austin TX (US) for applied materials, inc.
IPC Code(s): H01L21/673, C23C16/44, C23C16/455, C23C16/458, C23C16/52, C23C16/54, H01L21/67, H01L21/677
CPC Code(s): H01L21/67389
Abstract: disclosed are implementations for efficient purging of substrate carriers (and content held therein) and preventing external contaminants from entering a gas purge apparatus by coupling the gas purge apparatus to a substrate carrier, performing a first gas purging session of an environment of the substrate carrier, receiving a first signal of a first signal type, responsive to receiving the first signal, keeping the gas purge apparatus coupled to the substrate carrier, performing a second gas purging session of the environment of the substrate carrier, receiving a second signal of a second signal type, and, responsive to receiving the second signal, decoupling the purge apparatus from the substrate carrier.
Inventor(s): Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc., Shu-Kwan LAU of Sunnyvale CA (US) for applied materials, inc., Zuoming ZHU of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/687, H01L21/02, H01L21/67
CPC Code(s): H01L21/6875
Abstract: embodiments described herein relate to lift frames for central heating, and related processing chambers and methods. in one or more embodiments, a lift frame for positioning in a processing chamber applicable for use in semiconductor manufacturing includes a shaft. the shaft includes an opening formed in the shaft, and the shaft includes a first material. the lift frame includes a plurality of arms extending outwardly relative to the shaft, and an absorptive mass disposed in the opening of the shaft. the absorptive mass includes a second material having a higher absorptivity than the first material of the shaft.
20250038051. TUNGSTEN MOLYBDENUM STRUCTURES_simplified_abstract_(applied materials, inc.)
Inventor(s): Xi CEN of San Jose CA (US) for applied materials, inc., Kai WU of Palo Alto CA (US) for applied materials, inc., Dixiong WANG of Milpitas CA (US) for applied materials, inc., Yi LUO of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, C23C16/14, H01L21/285, H01L23/532
CPC Code(s): H01L21/76876
Abstract: a structure is provided including a substrate and a tungsten-containing layer. the tungsten-containing layer includes a nucleation layer disposed on the substrate and a bulk layer is disposed over the nucleation layer. the nucleation layer includes tungsten and the bulk layer includes about 0.1% to about 20% atomic molybdenum. the tungsten-containing layer includes a film stress of about 350 mpa to about 450 mpa.
20250038053. GROWTH CHAMBER SMART SEASONING_simplified_abstract_(applied materials, inc.)
Inventor(s): Zhepeng Cong of San Jose CA (US) for applied materials, inc., Tao Sheng of Fremont CA (US) for applied materials, inc., Ala Moradian of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/66, C23C16/52, C30B25/16, G05B13/02
CPC Code(s): H01L22/26
Abstract: a method of analyzing completion of seasoning of semiconductor processing chambers may include training a model using seasoning cycle characteristics data obtained from existing semiconductor processing chambers. a supervised learning process may label the characteristics data based on expert determined identify seasoning completion and may optionally label the characteristics data based on chamber open event information or preventive maintenance information. the trained model may be used to characterize another chamber during seasoning to determine whether seasoning is completed and/or when or how long or how many seasoning cycles may be performed until seasoning is complete.
Inventor(s): Prayudi LIANTO of Singapore (SG) for applied materials, inc., Marvin Louis BERNT of Whitefish MT (US) for applied materials, inc., Tapash CHAKRABORTY of Dombivali (IN) for applied materials, inc., Yin Wei LIM of Singapore (SG) for applied materials, inc., Jing XU of Kalispell MT (US) for applied materials, inc.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/03
Abstract: a method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. in some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (drie) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. in some embodiments, the deposited copper material in the structure has a < grain orientation normal to a horizontal surface of the structure.
20250039556. PULSED ILLUMINATION FOR FLUID INSPECTION_simplified_abstract_(applied materials, inc.)
Inventor(s): Asaf SCHLEZINGER of Modi'in (IL) for applied materials, inc.
IPC Code(s): H04N23/74, B65G47/22, G06T7/00, H04N7/015, H04N23/56
CPC Code(s): H04N23/74
Abstract: embodiments described herein provide for a method and system for the inspection of fluids for defects. a plurality of containers with fluids disposed therein are inspected for defects in an inspection system. a timing sequence is used to control the timing of light pulses directed to the fluid residing in the plurality of containers. a high-resolution camera is utilized to obtain images of the fluid disposed in the plurality of containers. an illumination time of pulses of light in the inspection zone is less than an exposure time of each frame of a plurality of frames of the high-resolution camera. as such, the inspection system and method of utilizing the inspection system allows for high-resolution images of the fluid to be captured without smearing of the defects in the captured images.
Inventor(s): Veeraraghavan S. BASKER of Schenectady NY (US) for applied materials, inc., Gregory COSTRINI of Flanders NJ (US) for applied materials, inc., Ashish PAL of San Ramon CA (US) for applied materials, inc., Benjamin COLOMBEAU of Salem MA (US) for applied materials, inc., Balasubramanian PRANATHARTHIHARAN of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L29/775, H01L21/762, H01L21/768, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/775
Abstract: a method of forming a portion of a gate-all-around field-effect transistor (gaa fet) includes forming placeholders, each interfacing with an extension region via a cap layer, in recesses formed in portions of a substrate isolated by shallow trench isolations (stis), the recesses extending into an inter-layer dielectric (ild) formed on the substrate, removing the placeholders selectively to the substrate, the cap layers, and the stis, forming selective cap layers at bottoms of the recesses, performing a substrate removal process to isotropically etch the substrate within the recesses, performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses, sculpting the spacer on sidewalls of the substrate and the stis within the recesses, performing a cap layer removal process to remove the cap layers within the recesses, and forming metal contacts within the recesses.
Inventor(s): Yan ZHANG of Westford MA (US) for applied materials, inc., Taegon KIM of Gloucester MA (US) for applied materials, inc., Johannes M. VAN MEER of Middleton MA (US) for applied materials, inc., Vikram M. BHOSLE of North Reading MA (US) for applied materials, inc., Jae Young LEE of Bedford MA (US) for applied materials, inc., Naushad K. VARIAM of Marblehead MA (US) for applied materials, inc.
IPC Code(s): H01L29/423, H01L21/768, H01L29/06, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: approaches herein provide devices and methods for forming gate-all-around transistors with improved gate spacer k-values. one method may include forming a gate-all-around (gaa) stack including a plurality of alternating first layers and second layers, and forming a source/drain (s/d) cavity through the plurality of alternating first layers and second layers. the method may further include forming an inner spacer in the s/d cavity, adjacent the plurality of alternating first layers and second layers, performing a first implant by directing fluorine ions to the gaa stack, through the s/d cavity, wherein the first implant is performed at a temperature greater than 30� celsius and forming a s/d material in the s/d cavity following the first implant.
Inventor(s): Dejiu Fan of Mountain View CA (US) for applied materials, inc., Yun-Chu Tsai of Taichung City (TW) for applied materials, inc., Sheng-Wen Wang of Tainan City (TW) for applied materials, inc., Dong Kil Yim of Pleasanton CA (US) for applied materials, inc., Soo Young Choi of Fremont CA (US) for applied materials, inc.
IPC Code(s): H01L29/786, C23C14/08, C23C14/58, C23C16/06, C23C16/455, C23C16/56, H01L21/02, H01L29/66
CPC Code(s): H01L29/7869
Abstract: embodiments described herein relate to engineering metal oxide layer interfaces to improve electronic device stability. for example, a transistor device can include a base structure and a metal oxide layer disposed on the base structure. the metal oxide layer includes at least one region having a gradient profile with respect to oxygen (o) composition.
Applied Materials, Inc. patent applications on January 30th, 2025
- Applied Materials, Inc.
- B23Q7/14
- B23Q11/14
- CPC B23Q7/1431
- Applied materials, inc.
- C08F20/56
- B24B37/22
- B24B37/24
- C08L39/06
- CPC C08F20/56
- C23C16/455
- C23C16/458
- CPC C23C16/45557
- C23C16/44
- C23C16/48
- H01L21/677
- CPC C23C16/45561
- F16K1/36
- F16K1/42
- F16K27/02
- CPC F16K1/36
- F16K27/00
- F15B13/08
- F15B19/00
- F16K37/00
- CPC F16K27/003
- G01N21/55
- C30B25/16
- CPC G01N21/55
- G01R19/12
- H01L21/66
- CPC G01R19/12
- H01J37/32
- CPC H01J37/32183
- CPC H01J37/32403
- H01L21/67
- CPC H01J37/32449
- CPC H01J37/32458
- CPC H01J37/32495
- CPC H01J37/32825
- CPC H01J37/32862
- H01L21/02
- CPC H01L21/02164
- C23C16/34
- C23C16/56
- H10B41/27
- H10B41/35
- H10B43/27
- H10B43/35
- CPC H01L21/0217
- H01L21/3205
- CPC H01L21/0234
- H01L21/306
- CPC H01L21/02532
- H01L21/04
- H01L21/266
- H01L29/40
- CPC H01L21/0475
- H01L21/687
- CPC H01L21/67259
- H01L21/673
- C23C16/52
- C23C16/54
- CPC H01L21/67389
- CPC H01L21/6875
- H01L21/768
- C23C16/14
- H01L21/285
- H01L23/532
- CPC H01L21/76876
- G05B13/02
- CPC H01L22/26
- H01L23/00
- CPC H01L24/03
- H04N23/74
- B65G47/22
- G06T7/00
- H04N7/015
- H04N23/56
- CPC H04N23/74
- H01L29/775
- H01L21/762
- H01L29/423
- H01L29/66
- H01L29/786
- CPC H01L29/775
- H01L29/06
- CPC H01L29/42392
- C23C14/08
- C23C14/58
- C23C16/06
- CPC H01L29/7869