Applied Materials, Inc. patent applications on January 2nd, 2025
Patent Applications by Applied Materials, Inc. on January 2nd, 2025
Applied Materials, Inc.: 21 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01L21/02 (4), H01J37/32 (3), H01L21/768 (3), H01L21/67 (3), H01L21/321 (2) B24B37/046 (1), H01L21/02118 (1), H01L22/12 (1), H01L21/76879 (1), H01L21/67248 (1)
With keywords such as: layer, chamber, semiconductor, portion, processing, substrate, include, gas, methods, and component in patent application abstracts.
Patent Applications by Applied Materials, Inc.
Inventor(s): Kevin H. Song of San Jose CA (US) for applied materials, inc., Benedict W. Pang of Burlingame CA (US) for applied materials, inc.
IPC Code(s): B24B37/04, B24B57/02, H01L21/3105, H01L21/321
CPC Code(s): B24B37/046
Abstract: exemplary substrate electrochemical planarization apparatuses may include a chuck body defining a substrate support surface. the apparatuses may include a retaining wall extending from the chuck body. the apparatuses may include an electrolyte delivery port disposed radially inward of the retaining wall. the apparatuses may include a spindle that is positionable over the chuck body. the apparatuses may include an end effector coupled with a lower end of the spindle. the end effector may be conductive. the apparatuses may include an electric contact extending from the chuck body or retaining wall. the apparatuses may include a current source. the current source may be configured to provide an electric current to an electrolyte within an open interior defined by the retaining wall.
Inventor(s): Nitin Deepak of Thane (IN) for applied materials, inc., Ryan Sheil of Santa Cruz CA (US) for applied materials, inc., Katherine Woo of Santa Clara CA (US) for applied materials, inc., Juan Carlos Rocha-Alvarez of San Carlos CA (US) for applied materials, inc., Jennifer Y. Sun of Fremont CA (US) for applied materials, inc.
IPC Code(s): C23C16/40, C23C16/34
CPC Code(s): C23C16/403
Abstract: exemplary processing methods may include providing a component for semiconductor processing to a processing region of a processing chamber. the methods may include providing one or more interface deposition precursors to the processing region. the methods may include depositing a layer of interface material on the component for semiconductor processing in the processing region. the methods may include providing one or more coating deposition precursors to the processing region. the methods may include depositing a layer of coating material on the component for semiconductor processing in the processing region.
Inventor(s): Andrea Leoncini of Singapore (SG) for applied materials, inc., Yi Kun Kelvin Goh of Singapore (SG) for applied materials, inc.
IPC Code(s): C23C16/458, C23C16/44, C23C16/46
CPC Code(s): C23C16/4586
Abstract: embodiments of the disclosure relate to heating jackets comprising a reformable insulator. the insulator may be shaped to conform to the shape of a vapor deposition precursor delivery system, or a portion thereof, and subsequently reformed to a different vapor deposition precursor delivery system, or a portion thereof. some embodiments of the disclosure combine multiple heating modules to form a heating jacket. the heating modules contain a flexible heating element and an insulating, protective cover.
Inventor(s): Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc., Zhepeng CONG of San Jose CA (US) for applied materials, inc., Vishwas Kumar PANDEY of Madhya Pradesh (IN) for applied materials, inc., Tao SHENG of Santa Clara CA (US) for applied materials, inc., Nimrod SMITH of Cupertino CA (US) for applied materials, inc., Karthik RAMANATHAN of Bangalore (IN) for applied materials, inc., Manjunath SUBBANNA of Bangalore (IN) for applied materials, inc.
IPC Code(s): C30B25/16, C30B25/10, G01K1/02, G01K3/08
CPC Code(s): C30B25/16
Abstract: a method and apparatus for virtually sensing a temperature of a hardware component of semiconductor processing chamber are disclosed. in one or more embodiments, a method of operation for a processing chamber suitable for use in semiconductor manufacturing includes receiving a process recipe for a manufacturing process and monitoring a first temperature of a first hardware component of the processing chamber using a sensor. the method further includes synthesizing, using a model of the processing chamber, a first virtual temperature of a second hardware component of the processing chamber based on the received process recipe and the first temperature of the first hardware component.
Inventor(s): Andrew Thomas Koll of West Linn OR (US) for applied materials, inc., Ayra Mae Sears of Portland OR (US) for applied materials, inc., Jered Dean Richter of Beaverton OR (US) for applied materials, inc.
IPC Code(s): G01B11/24, G01B11/25
CPC Code(s): G01B11/2441
Abstract: a precision motion characterization system includes an interferometer configured to emit a laser beam, a first object coupled to a non-moving portion of a linear actuator, and a second object coupled to a moving body of the linear actuator. the first object is configured to reflect a first portion of the laser beam and the second object is configured to reflect a second portion of the laser beam, and a processor is to perform operations including receiving a first image comprising a plurality of first linear interference fringes corresponding to the first portion of the laser beam, determining a first characteristic of the plurality of first linear interference fringes, receiving a second image comprising a plurality of second linear interference fringes corresponding to the second portion of the laser beam, and determining a second characteristic of the plurality of second linear interference fringes.
Inventor(s): Manoj Kumar Dayyala of Newark CA (US) for applied materials, inc., Jorge Pablo Fernandez of Saratoga CA (US) for applied materials, inc., Kourosh Nafisi of San Jose CA (US) for applied materials, inc.
IPC Code(s): G01B15/04, G03F7/00, G06T7/00, H01L21/66
CPC Code(s): G01B15/04
Abstract: disclosed herein are methods and systems for analyzing a cross-sectional feature of a structural element on a semiconductor wafer to determine whether an isolated or a systemic failure to reach preselected parameters occurred.
Inventor(s): Zhepeng CONG of San Jose CA (US) for applied materials, inc., Tao SHENG of Santa Clara CA (US) for applied materials, inc., Khokan C. PAUL of Cupertino CA (US) for applied materials, inc., Ashur J. ATANOS of San Jose CA (US) for applied materials, inc., Nimrod SMITH of Cupertino CA (US) for applied materials, inc., Vinh N. TRAN of San Jose CA (US) for applied materials, inc.
IPC Code(s): G01J5/80, C30B25/10, C30B25/12
CPC Code(s): G01J5/80
Abstract: the present disclosure relates to chamber kits, systems, and methods for calibrating temperature sensors for semiconductor manufacturing. in one or more embodiments, a chamber kit for processing chambers applicable for semiconductor manufacturing includes a plate formed of a transparent material. the plate includes an opening formed in an outer face of the plate. the chamber kit includes a first calibration substrate positioned at least partially in the opening of the plate, and the first calibration substrate is formed of a first material. the chamber kit includes a second calibration substrate positioned at least partially in the opening of the plate, and the second calibration substrate is formed of a second material that is different than the first material.
Inventor(s): Atilla Kilicarslan of Mountain View CA (US) for applied materials, inc., Raechel Chu-Hui Tan of Oakland CA (US) for applied materials, inc., Brooke Elise Montgomery of Morgan Hill CA (US) for applied materials, inc., Paul Z. Wirth of Kalispell MT (US) for applied materials, inc.
IPC Code(s): G05B19/18
CPC Code(s): G05B19/188
Abstract: a method includes determining, based at least in part on disturbance data, an actuation value associated with compensating for disturbance in a processing chamber. the method further includes associating the actuation value with an identifier corresponding to a recipe operation. the actuation value is to be retrieved, via the identifier, for subsequent execution of the recipe operation. the method further includes causing, based on retrieval of the actuation value via the identifier, actuation of one or more components of the processing chamber during a subsequent execution of the recipe operation to compensate for the disturbance.
Inventor(s): Pratik Champalal Kotcher of Chantilly VA (US) for applied materials, inc.
IPC Code(s): G05B19/418, G06F18/2135
CPC Code(s): G05B19/41865
Abstract: data associated with a first process performed for one or more substrates is identified. an amount of drift of a first set of metrology measurement values for the one or more substrates following completion of the first process and/or the second process from target values is determined. modifications to a recipe for the second process is determined in view of the determined amount of drift. the second process is updated based on the determined one or more modifications.
Inventor(s): Yang YANG of Cupertino CA (US) for applied materials, inc., Kartik RAMASWAMY of San Jose CA (US) for applied materials, inc., Fernando SILVEIRA of Livermore CA (US) for applied materials, inc., Imad YOUSIF of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32357
Abstract: methods and apparatus for a point of use remote plasma source are provided. in embodiments, a remote plasma apparatus includes: an enclosure surrounding a cavity; a first conductor surrounding a first portion of the enclosure; a second conductor surrounding a second portion of the enclosure, wherein the first portion of the enclosure and the second portion of the enclosure overlap by an overlap amount, and wherein each of the first conductor and the second conductor are circumferentially discontinuous; a dielectric layer disposed between and separating the first conductor and the second conductor; a gas inlet configured to flow a gas into the cavity; and a gas outlet disposed in a bottom of the enclosure and configured to flow the gas out of the cavity.
Inventor(s): Naomi YOSHIDA of Sunnyvale CA (US) for applied materials, inc., Nobuyuki SASAKI of Santa Clara CA (US) for applied materials, inc., Yoichi SUZUKI of Funabashi-shi (JP) for applied materials, inc., Tomoyuki TADA of Chiba (JP) for applied materials, inc., Balasubramanian PRANATHARTHIHARAN of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, C23C16/02, C23C16/24, C23C16/34, C23C16/40, C23C16/50, H01L21/768
CPC Code(s): H01J37/32899
Abstract: a cluster tool for forming an interconnection structure includes a pre-clean chamber, a selective chemical vapor deposition (cvd) chamber, a plasma-enhanced cvd (pecvd) chamber, one or more transfer chambers coupled to the pre-clean chamber, the selective cvd chamber, and the pecvd chamber, and configured to transfer the interconnection structure between the pre-clean chamber, the selective cvd chamber, and the pecvd chamber without breaking vacuum environment, and a controller configured to cause pre-cleaning of an exposed surface of a metal layer formed within a first dielectric layer of the interconnection structure in the pre-clean chamber, selective deposition of a cap layer on the pre-cleaned surface of the metal layer in the selective cvd chamber, and deposition of deposit a second dielectric layer on the cap layer and an exposed surface of the first dielectric layer in the pecvd chamber.
Inventor(s): Mark Saly of Santa Clara CA (US) for applied materials, inc., Feng Q. Liu of San Jose CA (US) for applied materials, inc., Bhaskar Jyoti Bhuyan of San Jose CA (US) for applied materials, inc., Jeffrey W. Anthis of San Jose CA (US) for applied materials, inc., David Thompson of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/311
CPC Code(s): H01L21/02118
Abstract: embodiments of the disclosure relate to methods of selectively depositing polysilicon after forming a flowable polymer film to protect a substrate surface within a feature. a first silicon (si) layer is deposited by physical vapor deposition (pvd). the flowable polymer film is formed on the first silicon (si) layer on the bottom. a portion of the first silicon (si) layer is selectively removed from the top surface and the at least one sidewall. the flowable polymer film is removed. in some embodiments, a second silicon (si) layer is selectively deposited on the first silicon (si) layer to fill the feature. in some embodiments, the remaining portion of the first silicon (si) layer on the bottom is oxidized to form a first silicon oxide (siox) layer on the bottom, and a silicon (si) layer or a second silicon oxide (siox) layer is deposited on the first silicon oxide (siox) layer.
Inventor(s): Daemian Raj BENJAMIN RAJ of Fremont CA (US) for applied materials, inc., Gregory Eugene CHICHKANOFF of Mountain View CA (US) for applied materials, inc., Shailendra SRIVASTAVA of Fremont CA (US) for applied materials, inc., Sai Susmita ADDEPALLI of San Jose CA (US) for applied materials, inc., Nikhil Sudhindrarao JORAPUR of Sunnyvale CA (US) for applied materials, inc., Abhigyan KESHRI of Sunnyvale CA (US) for applied materials, inc., Allison YAU of Cupertino CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, C23C16/455, C23C16/458, C23C16/50, H01J37/32, H10B41/20, H10B43/20
CPC Code(s): H01L21/022
Abstract: in one example, a process chamber comprises a lid assembly, a first gas supply, second gas supply, a chamber body, and a substrate support. the lid assembly comprises a gas box, a gas conduit passing through the gas box, a blocker plate, and a showerhead. the gas box comprises a gas distribution plenum, and a distribution plate comprising a plurality of holes aligned with the gas distribution plenum. the blocker plate is coupled to the gas box forming a first plenum. the showerhead is coupled to the blocker plate forming a second plenum. the first gas supply is coupled to the gas distribution plenum, and the second gas supply system is coupled to the gas conduit. the chamber body is coupled to the showerhead, and the substrate support assembly is disposed within an interior volume of the chamber body, and is configured to support a substrate during processing.
20250006499. INTEGRATED DIPOLE REGION FOR TRANSISTOR_simplified_abstract_(applied materials, inc.)
Inventor(s): Srinivas Gandikota of Santa Clara CA (US) for applied materials, inc., Yixiong Yang of Fremont CA (US) for applied materials, inc., Steven C.H. Hung of Sunnyvale CA (US) for applied materials, inc., Tianyi Huang of Santa Clara CA (US) for applied materials, inc., Seshadri Ganguli of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/28, H01L21/324, H01L21/8238
CPC Code(s): H01L21/28088
Abstract: methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. the electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-� dielectric layer on the metal film. in some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-� dielectric layer on the interfacial layer, and a metal film on the high-� dielectric layer. in some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-� dielectric layer.
Inventor(s): Yi ZHENG of Sunnyvale CA (US) for applied materials, inc., Xiaozhou CHE of Santa Clara CA (US) for applied materials, inc., Qiang MA of Cupertino CA (US) for applied materials, inc., Jun FANG of Xi'an (CN) for applied materials, inc.
IPC Code(s): H01L21/324, H01L21/02
CPC Code(s): H01L21/324
Abstract: a method of forming a capping layer on a substrate for annealing processes incorporates an interfacial layer of a material that is at least one element of a chemical compound used in the substrate. in some embodiments, the method may comprise depositing an interfacial layer on the substrate where the interfacial layer is amorphous silicon (a-si), amorphous sic, or amorphous sicn (where x is greater than zero to approximately 2), depositing an amorphous carbon (a-c) capping layer on the substrate, and annealing the substrate at a temperature of approximately 1500 degrees celsius or higher. the interfacial layer may have a thickness of approximately 5 nanometers to approximately 100 nanometers and may be formed on planar structures or on three-dimensional structures.
Inventor(s): Shiyu YUE of Santa Clara CA (US) for applied materials, inc., Wei LEI of San Jose CA (US) for applied materials, inc., Yu LEI of Belmont CA (US) for applied materials, inc., Ju Hyun OH of San Jose CA (US) for applied materials, inc., Zhimin QI of Santa Clara CA (US) for applied materials, inc., Sahil Jaykumar PATEL of Sunnyvale CA (US) for applied materials, inc., Yi XU of San Jose CA (US) for applied materials, inc., Aixi ZHANG of Santa Clara CA (US) for applied materials, inc., Bingqian LIU of Santa Clara CA (US) for applied materials, inc., Cong TRINH of Santa Clara CA (US) for applied materials, inc., Xianmin TANG of San Jose CA (US) for applied materials, inc., Hayrensa ABLAT of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/321, H01L21/768, H01L23/532
CPC Code(s): H01L21/67034
Abstract: embodiments herein relate to a method, semiconductor device structures, and multi-chamber processing system for exposing a semiconductor device structure to an oxidizing plasma to form an oxide layer on at least one electrical connection formed in at least one feature formed within a dielectric layer of the semiconductor device structure, performing an etch process to remove the oxide layer and form an etch recess between a portion of the electrical connection and the dielectric layer at least a portion of the etch recess extends underneath at least a portion of the dielectric layer, and filling the at least one feature and the etch recess with a metal material.
Inventor(s): Kyle M. Hanson of Kalispell MT (US) for applied materials, inc., Eric J. Bergman of Kalispell MT (US) for applied materials, inc., Gregory J. Wilson of Kalispell MT (US) for applied materials, inc., Paul R. McHugh of Kalispell MT (US) for applied materials, inc., Benjamin Clay Bradley of Kalispell MT (US) for applied materials, inc., Aaron Paul Juntunen of Kalispell MT (US) for applied materials, inc., Deepak Saagar Kalaikadal of Kalispell MT (US) for applied materials, inc., Daniel Durado of Kalispell MT (US) for applied materials, inc., Carl Campbell Stringer of Whitefish MT (US) for applied materials, inc., James Jay Tripp of Kalispell MT (US) for applied materials, inc., Jason A. Rye of Kalispell MT (US) for applied materials, inc., John L. Klocke of Kalispell MT (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/02, H01L21/673
CPC Code(s): H01L21/67051
Abstract: method and systems for cleaning and wetting a semiconductor substrate, are provided. methods and systems include forming an atmosphere in a basin housing the semiconductor substrate with a gas having a higher solubility in a wetting agent than oxygen. methods and systems include spraying the wetting agent with a spray head onto the substrate while maintaining the atmosphere. methods and systems include rotationally translating the semiconductor substrate, the spray head, or both the semiconductor substrate and the spray head, methods and systems include wetting a plurality of features defined in the substrate.
Inventor(s): Zhepeng CONG of San Jose CA (US) for applied materials, inc., Alain DUBOUST of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, G05B19/04
CPC Code(s): H01L21/67248
Abstract: a non-transitory computer readable medium to thermally adjust a chamber component is disclosed therein. the non-transitory computer readable medium includes instructions that when executed cause a plurality of operations to be conducted. the operations include sensing a first temperature of the chamber component within a semiconductor processing chamber, comparing the first temperature to a first set-point of the chamber component, and adjusting a purge gas flowrate of a purge gas supplied to a portion of the processing chamber. the plurality of operations include sensing a second temperature of a reflector component in the portion of the semiconductor processing chamber, comparing the second temperature of the reflector component to a second set-point of the reflector component, and initiating a reflector cooling operation within the reflector component when the second temperature exceeds the second set-point. the portion is at least partially physically isolated from a processing portion by a thermally transmissive window.
Inventor(s): Feng Q. Liu of San Jose CA (US) for applied materials, inc., Xinke Wang of Singapore (SG) for applied materials, inc., Liqi Wu of San Jose CA (US) for applied materials, inc., Qihao Zhu of Sunnyvale CA (US) for applied materials, inc., Bhaskar Jyoti Bhuyan of San Jose CA (US) for applied materials, inc., Mark Saly of Santa Clara CA (US) for applied materials, inc., David Thampson of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/768
CPC Code(s): H01L21/76879
Abstract: embodiments of the disclosure relate to methods of selectively depositing a metal after use of a flowable polymer to protect a substrate surface within a feature. a first metal layer is deposited by physical vapor deposition (pvd). the semiconductor substrate surface is exposed to one or more monomers to form a flowable and flexible polymer film on the first metal layer within the at least one feature. the flowable polymer film forms on the first metal layer on the bottom. the one or more monomers are selected from one or more of amines with bi-functional groups, aldehydes with bi-functional groups, cyanates with bi-functional groups, ketones with bi-functional groups, and alcohols with bi-functional groups. at least a portion of the first metal layer is selectively removed from the top surface and the at least one sidewall. the flowable polymer film is removed.
Inventor(s): Milan Pesic of Paoli PA (US) for applied materials, inc.
IPC Code(s): H01L21/66, H01L29/24
CPC Code(s): H01L22/12
Abstract: a method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. the method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from entering a conduction band of the semiconductor layer and instead causes current to flow through defects in the semiconductor layer. the method may also include characterizing the defects in the semiconductor layer based on the current flowing through the defects in the semiconductor layer.
Inventor(s): Zongkai WU of Santa Clara CA (US) for applied materials, inc., Pei Chia CHEN of Tokyo (JP) for applied materials, inc., Wen-Hao WU of San Jose CA (US) for applied materials, inc., Jungmin LEE of Santa Clara CA (US) for applied materials, inc., Chung-chia CHEN of Hsinchu City (TW) for applied materials, inc., Yu-Hsin LIN of Zhubei City (TW) for applied materials, inc., Kevin CHEN of Santa Clara CA (US) for applied materials, inc., Wenhui LI of Santa Clara CA (US) for applied materials, inc., Yu-Min WANG of Tainan City (TW) for applied materials, inc., Lai ZHAO of Campbell CA (US) for applied materials, inc., Soo Young CHOI of Fremont CA (US) for applied materials, inc.
IPC Code(s): H10K59/80, H10K59/12, H10K59/122
CPC Code(s): H10K59/8731
Abstract: sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display, such as an organic light-emitting diode (oled) display, are provided. in one example, a sub-pixel includes a substrate, adjacent overhang structures, an anode, an oled material, a cathode, an encapsulation layer stack. the encapsulation layer stack includes a first layer, a second layer disposed over the first layer, and a third layer. the first layer and the second layer have a first portion disposed over the cathode, a second portion disposed over a sidewall of each overhang structure, and a third portion disposed under an underside surface of an extension of each overhang structure. a gap is defined by contact of the first portion of the second layer and the third portion of the second layer. the third layer is disposed over the second layer outside of the gap.
Applied Materials, Inc. patent applications on January 2nd, 2025
- Applied Materials, Inc.
- B24B37/04
- B24B57/02
- H01L21/3105
- H01L21/321
- CPC B24B37/046
- Applied materials, inc.
- C23C16/40
- C23C16/34
- CPC C23C16/403
- C23C16/458
- C23C16/44
- C23C16/46
- CPC C23C16/4586
- C30B25/16
- C30B25/10
- G01K1/02
- G01K3/08
- CPC C30B25/16
- G01B11/24
- G01B11/25
- CPC G01B11/2441
- G01B15/04
- G03F7/00
- G06T7/00
- H01L21/66
- CPC G01B15/04
- G01J5/80
- C30B25/12
- CPC G01J5/80
- G05B19/18
- CPC G05B19/188
- G05B19/418
- G06F18/2135
- CPC G05B19/41865
- H01J37/32
- CPC H01J37/32357
- C23C16/02
- C23C16/24
- C23C16/50
- H01L21/768
- CPC H01J37/32899
- H01L21/02
- H01L21/311
- CPC H01L21/02118
- C23C16/455
- H10B41/20
- H10B43/20
- CPC H01L21/022
- H01L21/28
- H01L21/324
- H01L21/8238
- CPC H01L21/28088
- CPC H01L21/324
- H01L21/67
- H01L23/532
- CPC H01L21/67034
- H01L21/673
- CPC H01L21/67051
- G05B19/04
- CPC H01L21/67248
- CPC H01L21/76879
- H01L29/24
- CPC H01L22/12
- H10K59/80
- H10K59/12
- H10K59/122
- CPC H10K59/8731