Applied Materials, Inc. patent applications on January 23rd, 2025
Patent Applications by Applied Materials, Inc. on January 23rd, 2025
Applied Materials, Inc.: 17 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01L21/02 (4), C23C16/455 (3), H01L21/67 (3), G03F7/00 (3), G03F7/004 (2) C23C16/45529 (1), G05B19/41865 (1), H01L21/68 (1), H01L21/67253 (1), H01L21/6719 (1)
With keywords such as: substrate, processing, include, methods, surface, precursor, reflective, semiconductor, layer, and support in patent application abstracts.
Patent Applications by Applied Materials, Inc.
Inventor(s): Yogesh Tomar of Madhya Pradesh (IN) for applied materials, inc., Nikshep Patil of Vidya Nagar (IN) for applied materials, inc., Kirubanandan Shanmugam Naina of Whitefield (IN) for applied materials, inc., Hanish Kumar Panavalappil Kumarankutty of Malur (IN) for applied materials, inc., Gayatri Natu of Mumbai (IN) for applied materials, inc., Mahesh Chelvaraj Arcot of Maharashtra (IN) for applied materials, inc., Senthil Kumar Nattamai Subramanian of Hosur (IN) for applied materials, inc., Hari Venkatesh Rajendran of Hosur (IN) for applied materials, inc., Michael Rice of Pleasanton CA (US) for applied materials, inc., Christopher Laurent Beaudry of San Jose CA (US) for applied materials, inc.
IPC Code(s): C23C16/455, C23C16/44, C23C16/52
CPC Code(s): C23C16/45529
Abstract: a method includes performing an atomic layer deposition (ald) process with respect to a plurality of target elements to coat interiors of the plurality of target elements with a protective coating. performing the ald process includes alternating delivery of a first precursor inside the plurality of target elements for a first duration to form an adsorption layer on the interiors of the plurality of target elements, alternating purging of the first precursor from the plurality of target elements for a second duration, and alternating delivery of a second precursor inside the plurality of target elements for a third duration to cause the second precursor to react with the adsorption layer and form a target layer on the interiors of the plurality of target elements.
Inventor(s): David Marquardt of Scottsdale AZ (US) for applied materials, inc.
IPC Code(s): C23C16/455, C23C16/448, H01L21/02
CPC Code(s): C23C16/45561
Abstract: ampoules including a solid volume of the semiconductor chemical precursor and methods of use and manufacturing are described. the solid volume of the semiconductor chemical precursor includes an ingress opening, at least one flow channel, and an outlet passage that are in fluid communication with each other. the solid volume of the semiconductor manufacturing precursor is made of a porous or alternatively a non-porous material. a flow path is defined by at least one flow channel through which a carrier gas flows in contact with the solid volume of the semiconductor chemical precursor.
Inventor(s): Tetsuya ISHIKAWA of San Jose CA (US) for applied materials, inc., Kim Ramkumar VELLORE of San Jose CA (US) for applied materials, inc.
IPC Code(s): C23C16/46, G05D23/27
CPC Code(s): C23C16/46
Abstract: the present disclosure relates to methods of adjusting uniformity for substrate processing, and related apparatus and systems, for semiconductor manufacturing. in one or more embodiments, a heating power applied to a set of one or more heat sources is adjusted by an adjustment factor. in one or more embodiments, a method of adjusting uniformity. the method includes scanning a sensor across one or more sections to take a plurality of readings, generating a signal profile including the plurality of readings, and analyzing the signal profile by comparing the signal profile to a range. the method includes adjusting one or more heating parameters if at least one portion of the signal profile is outside of the range. the adjusting includes identifying a set of one or more heat sources that correlate with the at least one portion of the signal profile, and adjusting a heating power by an adjustment factor.
20250027716. IMPROVED REFLECTOR FOR PROCESS CHAMBER_simplified_abstract_(applied materials, inc.)
Inventor(s): Raja Murali DHAMODHARAN of Madurai (IN) for applied materials, inc., Shu-Kwan LAU of Sunnyvale CA (US) for applied materials, inc., Shainish NELLIKKA of Bangalore (IN) for applied materials, inc., Enle CHOO of Saratoga CA (US) for applied materials, inc., Kalaivanan MOHANADASS of Santa Clara CA (US) for applied materials, inc., Aniketnitin PATIL of San Jose CA (US) for applied materials, inc.
IPC Code(s): F27B17/00, H01L21/67, H05B3/00
CPC Code(s): F27B17/0025
Abstract: a modular reflective heating system for use in a process chamber is provided. the modular reflective heating system includes: a plurality of connectors; a plurality of lamps, each lamp connected to at least one of the connectors; a reflector including: a base; and a reflective assembly including a first plurality of reflective portions and a second plurality of reflective portions. each reflective portion in the first plurality of reflective portions and the second plurality of reflective portions is connected to the base, and each reflective portion in the first plurality of reflective portions and the second plurality of reflective portions is configured to be individually disconnected from the base. the modular reflective heating system further includes a spare reflective portion configured to replace a first reflective portion in the first plurality of reflective portions or the second plurality of reflective portions.
Inventor(s): Srikanth V. Racherla of Fremont CA (US) for applied materials, inc., Ashish Singh Raichur of San Jose CA (US) for applied materials, inc., Jaeyoung Kim of Yongin-si (KR) for applied materials, inc., Makoto Inagawa of Palo Alto CA (US) for applied materials, inc.
IPC Code(s): G01N21/956, G01N21/88, G01N21/95, G01N35/00
CPC Code(s): G01N21/95684
Abstract: a load lock system including an imaging subsystem and an image processing subsystem to capture comprehensive data of a substrate within a load lock chamber. the imaging subsystem can include multiple imaging elements (e.g. cameras or image sensors), to capture image data of a substrate. the image processing subsystem can process the image data with a number of computer vision, or feature extraction techniques to identify nonconformities associated with the substrate. these nonconformities can include chips, breaks, scratch, placement errors, orientation errors, or a number of other errors associated with the substrate and substrate components. the image processing subsystem can further output a message indicating any one of these errors have occurred.
Inventor(s): TZU SHUN YANG of Milpitas CA (US) for applied materials, inc., ZHENXING HAN of Sunnyvale CA (US) for applied materials, inc., MADHUR SACHAN of Belmont CA (US) for applied materials, inc., LEQUN LIU of San Jose CA (US) for applied materials, inc., NASRIN KAZEM of Santa Clara CA (US) for applied materials, inc., LAKMAL CHARIDU KALUTARAGE of San Jose CA (US) for applied materials, inc., MARK JOSEPH SALY of Milpitas CA (US) for applied materials, inc.
IPC Code(s): G03F7/004, G03F7/00, G03F7/16, G03F7/36, H01L21/027
CPC Code(s): G03F7/0042
Abstract: embodiments disclosed herein may include a method for developing a photopatterned metal oxo photoresist. in an embodiment, the method may include pre-treating the photopatterned metal oxo photoresist with a pre-treatment process, developing the photopatterned metal oxo photoresist with a thermal dry develop process to selectively remove a portion of the photopatterned metal oxo photoresist and form a resist mask. in an embodiment, the thermal dry develop process includes a first sub-operation, and a second sub-operation that is different than the first sub-operation. in an embodiment, the process further includes post-treating the resist mask with a post-treatment process.
Inventor(s): NASRIN KAZEM of Santa Clara CA (US) for applied materials, inc., LAKMAL CHARIDU KALUTARAGE of San Jose CA (US) for applied materials, inc., MADHUR SACHAN of Belmont CA (US) for applied materials, inc., MARK SALY of Milpitas CA (US) for applied materials, inc., ANDREA LEONCINI of Santa Clara CA (US) for applied materials, inc., DOREEN WEI YING YONG of Singapore (SG) for applied materials, inc.
IPC Code(s): G03F7/30, G03F7/00, G03F7/004, G03F7/38
CPC Code(s): G03F7/30
Abstract: embodiments disclosed herein include a method of dry developing a metal-oxide photoresist. in an embodiment, a method of patterning a metal-oxide photoresist, such as a sn-based photoresist, includes depositing the metal-oxide photoresist over a substrate, exposing the metal-oxide photoresist with an extreme ultra-violet (euv) exposure to form exposed regions and non-exposed regions, and developing the exposed metal-oxide photoresist using an electron-donor ligand-based dry etch process.
Inventor(s): Thomas L. LAIDIG of Richmond CA (US) for applied materials, inc., Chi-Ming TSAI of San Jose CA (US) for applied materials, inc.
IPC Code(s): G03F7/00, G03F7/20
CPC Code(s): G03F7/70416
Abstract: a method is provided including directing a plurality of beams of radiation at a first area of a first layer on a substrate, each beam incident upon a different portion of a plurality of portions within the first area. each portion has an area of a first size, the plurality of beams of radiation are directed at the first area based on a first pattern, the first pattern comprises a plurality of unit cells that include a plurality of on cells and a plurality of off cells, each unit cell has an area smaller than the first size, the plurality of on cells identify locations within the first area at which a beam of radiation of the plurality of beams of radiation is centrally focused, and the plurality of off cells identify locations within the first area at which no beam of radiation of the plurality of beams of radiation is centrally focused.
Inventor(s): Piyush Kumar Pandey of Bangalore (IN) for applied materials, inc., Prabal Sen of Bangalore (IN) for applied materials, inc., Ganapathy Saravanavel of Madurai (IN) for applied materials, inc., Himadri Shekhar Hansda of Bangalore (IN) for applied materials, inc., Mohammed Dilkash Azam of Bangalore (IN) for applied materials, inc., Sidharth Bhatia of Santa Cruz CA (US) for applied materials, inc.
IPC Code(s): G05B19/18, G05B23/02
CPC Code(s): G05B19/188
Abstract: a method includes obtaining first data indicative of a measured profile of a substrate. the method further includes obtaining second data indicative of a profile of a reference substrate. the method further includes determining a corrected substrate profile based on the first data and the second data. the method further includes performing a corrective action based on the corrected substrate profile.
20250028304. QUEUE TIME CONTROL_simplified_abstract_(applied materials, inc.)
Inventor(s): Chongyang Wang of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): G05B19/418
CPC Code(s): G05B19/41865
Abstract: a method includes determining a predetermined queue time associated with a process recipe. the predetermined queue time is associated with an amount of time a substrate is at a location prior to being moved from the location. the method further includes causing control of speed associated with one or more components of a substrate processing system based on the predetermined queue time. the control of speed is associated with transfer of the substrate.
20250029816. HEATED METAL LID FOR SELECTIVE PECVD_simplified_abstract_(applied materials, inc.)
Inventor(s): Douglas Long of Sunnyvale CA (US) for applied materials, inc., Vinod Kumar Konda Purathe of Bangalore (IN) for applied materials, inc., Dien-Yeh Wu of San Jose CA (US) for applied materials, inc., Jallepally Ravi of San Ramon CA (US) for applied materials, inc., Hideaki Goto of Narashino-shi (JP) for applied materials, inc., Manjunatha Koppa of Bengaluru (IN) for applied materials, inc., Hiroyuki Takahama of Katori-shi (JP) for applied materials, inc., Shih Yao Hsu of Santa Clara CA (US) for applied materials, inc., Sandesh Yadamane Dharmaiah of Bangalore (IN) for applied materials, inc.
IPC Code(s): H01J37/32, C23C16/455
CPC Code(s): H01J37/32522
Abstract: gas distribution assemblies for a semiconductor manufacturing processing chamber comprising a first showerhead with a first flange and a second showerhead with a second flange. a first two-piece rf isolator comprises a first inner rf isolator spaced from a first outer rf isolator. the first inner rf isolator spaced from the first flange of the first showerhead to create a first flow path. a second two-piece rf isolator comprises a second inner rf isolator spaced from a second outer rf isolator. the second rf isolator spaced from the second flange of the second showerhead to create a second flow path. processing chambers incorporating the gas distribution assemblies, and processing methods using the gas distribution assemblies are also described.
Inventor(s): Ryan Ley of Mountain View CA (US) for applied materials, inc., Archana Kumar of Mountain View CA (US) for applied materials, inc., Michel El Khoury Maroun of Mountain View CA (US) for applied materials, inc., Benjamin D. Briggs of Merrimack NH (US) for applied materials, inc.
IPC Code(s): H01L21/02, C23C16/34, C23C16/50, H01J37/32
CPC Code(s): H01L21/0254
Abstract: exemplary semiconductor processing methods may include performing a treatment operation on a substrate housed within a first processing region of a first semiconductor processing chamber. the methods may include providing a nitrogen-containing precursor to the first processing region. the methods may include forming plasma effluents of the nitrogen-containing precursor. the methods may include contacting the substrate with the plasma effluents of the nitrogen-containing precursor. the contacting may nitride a surface of the substrate. the methods may include transferring the substrate from the first processing region of the first semiconductor processing chamber to a second processing region of a second semiconductor processing chamber. the methods may include providing one or more deposition precursors to the second processing region. the methods may include contacting the substrate with the one or more deposition precursors. the contacting may deposit a layer of dielectric material on the substrate.
Inventor(s): Jiayin Huang of Fremont CA (US) for applied materials, inc., Zihui Li of Santa Clara CA (US) for applied materials, inc., Anchuan Wang of San Jose CA (US) for applied materials, inc., Nitin K. Ingle of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/3065, H01L21/02
CPC Code(s): H01L21/3065
Abstract: exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing region of a semiconductor processing chamber. a first layer of silicon-and-germanium-containing material and a second layer of silicon-and-germanium-containing material may be disposed on a substrate housed within the processing region. a native oxide may be present on the first layer and the second layer. the methods may include contacting the substrate with the pre-treatment precursor to remove the native oxide. the methods may include providing an oxygen-containing precursor to the processing region. the methods may include contacting the substrate with the oxygen-containing precursor to oxidize at least a portion of the second layer. the methods may include providing an etchant precursor to the processing region. the methods may include contacting the substrate with the etchant precursor to selectively etch the first layer of silicon-and-germanium-containing material.
Inventor(s): Anish Janakiraman of Bangalore (IN) for applied materials, inc., Mayur Govind Kulkarni of Bangalore (IN) for applied materials, inc., Deenesh Padhi of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/687
CPC Code(s): H01L21/6719
Abstract: exemplary semiconductor processing chambers may include a chamber body. the chambers may include a substrate support within the chamber body. the substrate support may define a substrate support surface. the chambers may include a faceplate supported atop the chamber body. the substrate support and a bottom surface of the faceplate may at least partially define a processing region. the bottom surface of the faceplate may define an annular protrusion that is directly above at least a portion of a radially outer 10% of the substrate support surface and an annular groove that is positioned radially outward of the annular protrusion. at least a portion of the annular groove may extend radially outward beyond the substrate support surface. the faceplate may define apertures through the faceplate. a first subset of the apertures may extend through the annular protrusion and a second subset of the apertures may extend through the annular groove.
Inventor(s): Kim Ramkumar VELLORE of San Jose CA (US) for applied materials, inc., Tetsuya ISHIKAWA of San Jose CA (US) for applied materials, inc., Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/66, H01L21/687
CPC Code(s): H01L21/67253
Abstract: the present disclosure relates to methods of analyzing uniformity for substrate processing, and related apparatus and systems, for semiconductor manufacturing. in one or more embodiments, a non-uniformity is indicated, and the non-uniformity is a temperature non-uniformity and/or a physical non-uniformity. in one or more embodiments, a signal profile is accepted or rejected. in one or more embodiments, a method of analyzing uniformity for substrate processing applicable for semiconductor manufacturing includes heating an internal volume of a processing chamber using a target value. the method includes rotating a substrate support, and scanning, while rotating the substrate support, a sensor across one or more sections to take a plurality of readings. the method includes generating a signal profile including the plurality of readings, and analyzing the signal profile by comparing the signal profile to a range.
Inventor(s): Trung H. DAO of San Jose CA (US) for applied materials, inc., Sagir Bipin KADIWALA of Santa Clara CA (US) for applied materials, inc., Sam KIM of San Jose CA (US) for applied materials, inc., Minh Quoc TRAN of Gilroy CA (US) for applied materials, inc., Gu LIU of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L21/68, B25J9/16, G01B11/14, G06T7/80
CPC Code(s): H01L21/68
Abstract: methods, systems, and apparatus for measuring a gap between a support surface for a substrate and an opposing upper surface of a processing chamber. the methods comprise: disposing a sensor substrate at a location spaced between the support surface and the upper surface, the sensor substrate comprising a body having a first side and a second side opposite the first side, the first side facing the support surface and the second side facing the upper surface, the first side having a first sensor and the second side having a second sensor; measuring, using the first sensor, a first distance between the first side and the support surface; measuring, using the second sensor, a second distance between the second side and the upper surface; and determining a gap between the support surface and the upper surface using the first distance and the second distance.
Inventor(s): Roey Shaviv of Palo Alto CA (US) for applied materials, inc., Suketu Arun Parikh of San Jose CA (US) for applied materials, inc., Feng Chen of San Jose CA (US) for applied materials, inc., Lu Chen of Cupertino CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, H01L21/02
CPC Code(s): H01L21/76847
Abstract: provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. deposition is performed to selectively deposit on the unblocked insulating surfaces.
Applied Materials, Inc. patent applications on January 23rd, 2025
- Applied Materials, Inc.
- C23C16/455
- C23C16/44
- C23C16/52
- CPC C23C16/45529
- Applied materials, inc.
- C23C16/448
- H01L21/02
- CPC C23C16/45561
- C23C16/46
- G05D23/27
- CPC C23C16/46
- F27B17/00
- H01L21/67
- H05B3/00
- CPC F27B17/0025
- G01N21/956
- G01N21/88
- G01N21/95
- G01N35/00
- CPC G01N21/95684
- G03F7/004
- G03F7/00
- G03F7/16
- G03F7/36
- H01L21/027
- CPC G03F7/0042
- G03F7/30
- G03F7/38
- CPC G03F7/30
- G03F7/20
- CPC G03F7/70416
- G05B19/18
- G05B23/02
- CPC G05B19/188
- G05B19/418
- CPC G05B19/41865
- H01J37/32
- CPC H01J37/32522
- C23C16/34
- C23C16/50
- CPC H01L21/0254
- H01L21/3065
- CPC H01L21/3065
- H01L21/687
- CPC H01L21/6719
- H01L21/66
- CPC H01L21/67253
- H01L21/68
- B25J9/16
- G01B11/14
- G06T7/80
- CPC H01L21/68
- H01L21/768
- CPC H01L21/76847
