Applied Materials, Inc. patent applications on February 20th, 2025
Patent Applications by Applied Materials, Inc. on February 20th, 2025
Applied Materials, Inc.: 21 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01L21/02 (4), H01L21/67 (3), H01J37/32 (3), H01L21/3065 (3), H01L21/308 (2) B23K26/0622 (1), H01L21/0274 (1), H10B12/03 (1), H01L22/20 (1), H01L21/76867 (1)
With keywords such as: substrate, layer, processing, process, portion, material, wafer, further, device, and mask in patent application abstracts.
Patent Applications by Applied Materials, Inc.
Inventor(s): Gagandeep Singh Joshi of Ontario (CA) for applied materials, inc., Joseph Frederick Behnke of San Jose CA (US) for applied materials, inc., Joseph Frederick Sommers of Roseville CA (US) for applied materials, inc.
IPC Code(s): B23K26/0622
CPC Code(s): B23K26/0622
Abstract: a method includes determining first data indicative of processing parameters for processing a material in a laser processing system comprising a digital twin. the method further includes providing the first data as input to a trained machine learning model, wherein the digital twin comprises the trained machine learning model. the method further includes obtaining one or more outputs of the trained machine learning model, the one or more outputs indicating predicted performance data associated with the processing parameters for processing the material. the method further includes causing, based on the predicted performance data, the material to be processed according to the processing parameters.
Inventor(s): Andreas SAUER of GroĂostheim (DE) for applied materials, inc., Volker HACKER of Altenstadt-Oberau (DE) for applied materials, inc., Thomas DEPPISCH of Aschaffenburg (DE) for applied materials, inc., Ralf SCHEIDT of Wemmetsweiler (DE) for applied materials, inc.
IPC Code(s): C23C14/24, G01F11/28, H01M4/02, H01M4/04, H01M4/38, H01M10/052
CPC Code(s): C23C14/246
Abstract: a vapor deposition apparatus is provided. the vapor deposition apparatus includes a tank for providing a liquefied material, a first unit having an alterable first volume, the first unit including a first actuator and including a first line to be in fluid communication with the tank. further, the vapor deposition apparatus includes a second unit having an alterable second volume, the second unit including a second actuator and including a second line to be in fluid communication with the tank. the vapor deposition apparatus includes an evaporation arrangement, the evaporation arrangement being in fluid communication with the first unit and the second unit. the first actuator and the second actuator are configured to alternatingly provide a force to the alterable first volume and the alterable second volume for providing the liquefied material to the evaporation arrangement.
20250060041. MULTI-PIECE SLIT VALVE GATE_simplified_abstract_(applied materials, inc.)
Inventor(s): Farzad Vakilzadeh of San Jose CA (US) for applied materials, inc., Shawn Thanhson Le of Manteca CA (US) for applied materials, inc., Ofer Amir of Half Moon Bay CA (US) for applied materials, inc., Ramon Zaragoza of San Jose CA (US) for applied materials, inc.
IPC Code(s): F16K3/02
CPC Code(s): F16K3/0227
Abstract: disclosed is a slit valve gate. the slit valve gate includes a base portion configured to couple to a slit valve actuator and includes a first angled alignment feature. the slit valve gate further includes a seal portion coupled to the base portion. the seal portion is configured to create an airtight seal between the slit valve gate and a sealing surface of a slit valve opening. the slit valve gate further includes a clamp portion coupled to the base portion. the clamp portion includes a second angled alignment feature configured to interface with the first angled alignment feature of the base portion to align the clamp portion with respect to the base portion. the clamp portion retains the seal portion at least partially between the clamp portion and the base portion.
Inventor(s): Chang Ke of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): F16K31/06, B04C3/06, F16K37/00
CPC Code(s): F16K31/0655
Abstract: certain embodiments of the present disclosure relate to a gas flow valve. the gas flow valve includes a housing configured to receive a flow of gas. the gas flow valve further includes a plunger configured to move between a closed position and one or more open positions within the housing. the gas flow valve further includes a position sensor configured to measure a distance associated with a difference in position of the plunger between the closed position and the one or more open position. the gas flow valve further includes a force sensor coupled to the plunger and configured to measure a force exerted by the plunger in the closed position on a sealing surface.
20250060298. IN-SITU PARTICLE DETECTION_simplified_abstract_(applied materials, inc.)
Inventor(s): Wei Weng of Sunnyvale CA (US) for applied materials, inc., Chang Ke of Sunnyvale CA (US) for applied materials, inc., Changgong Wang of San Jose CA (US) for applied materials, inc.
IPC Code(s): G01N15/06, H01J37/32
CPC Code(s): G01N15/0656
Abstract: a processing system includes a processing chamber defining a processing region. a foreline is coupled with the processing chamber and defines a fluid conduit. a plasma trap is provided within an interior of the foreline to charge and trap at least some particles in the fluid conduit. the system further includes a particle detector to collect at least some of the charged particles and measure an electric charge produced by the particles.
Inventor(s): Elias Anthony Martinez of San Jose CA (US) for applied materials, inc., Sidharth Bhatia of Santa Cruz CA (US) for applied materials, inc., Sarah Michelle Bobek of Santa Clara CA (US) for applied materials, inc., Ka Shun Wong of San Jose CA (US) for applied materials, inc., Zhi Wang of Redwood City CA (US) for applied materials, inc., Martin J. Seamons of San Jose CA (US) for applied materials, inc., Raj Singu of San Jose CA (US) for applied materials, inc., Abdul Aziz Khaja of San Jose CA (US) for applied materials, inc., Ganesh Balasubramanian of Fremont CA (US) for applied materials, inc., Mark McTaggart Wylie of Meridian ID (US) for applied materials, inc.
IPC Code(s): G01N21/95, G01N35/00
CPC Code(s): G01N21/9505
Abstract: disclosed are systems and techniques for fast and efficient detection of defects in wafers, including a system that has a factory interface (fi) coupled to a wafer carrier and a load lock chamber. the fi includes a robot fetches a wafer from the wafer carrier and deliver the first wafer to an aligner device. the aligner device imparts rotational motion to the wafer and identifies, using the rotational motion of the wafer, a position of a reference feature of the wafer. the fi further includes an optical inspection system that collects, during the rotational motion imparted to the wafer, an imaging data for the first wafer. the system further includes a processing device that performs evaluation, using the imaging data, of a presence of defect(s) in the wafer, and evaluates suitability of the wafer for wafer processing.
Inventor(s): Varoujan Chakarian of Northridge CA (US) for applied materials, inc.
IPC Code(s): G06T7/00, G06V10/147
CPC Code(s): G06T7/0004
Abstract: a method includes grouping signal traces based on signal trace characteristics. the method includes generating an image, a first dimension of the image corresponding to the signal traces, and a second dimension of the image corresponding to time values, where a visual indicator corresponds to a signal trace characteristic of a signal trace at a time value, the signal trace corresponds to a row or column of the first dimension, and the time value corresponds the second dimension. the method includes detecting a defect in operation of components of manufacturing equipment associated with the signal traces based on a deviation of visual indicators in a row or column from a visual indicator of a respective group of visual indicators associated with signal traces with similar signal trace characteristics. the method includes classifying the defect based on a signal trace corresponding to the row or column of the image.
20250062104. HEATED PEDESTAL WITH LOW IMPEDANCE RF ROD_simplified_abstract_(applied materials, inc.)
Inventor(s): Sudhir R. GONDHALEKAR of Fremont CA (US) for applied materials, inc., Peter LAI of Santa Clara CA (US) for applied materials, inc., Suresh KARAVINAKOPPA of Bangalore (IN) for applied materials, inc., Pavankumar Ramanand HARAPANHALLI of Bangalore (IN) for applied materials, inc.
IPC Code(s): H01J37/32, H03H7/38
CPC Code(s): H01J37/32724
Abstract: embodiments of substrate supports for use in process chambers are provided herein. in some embodiments, a substrate support for a process chamber includes: a pedestal having a support surface for supporting a substrate, one or more heating elements disposed therein, and an rf electrode disposed therein; a hollow shaft coupled to a lower surface of the pedestal; and an rf rod extending through the hollow shaft and having an upper portion that includes an upper end coupled to the rf electrode, wherein the upper end of the rf rod has at least one of (a) a cross sectional width that is wider than a lower portion of the rf rod or (b) one or more slots.
Inventor(s): Martin Hilkene of Santa Clara CA (US) for applied materials, inc., Tobin Kaufman-Osborn of Santa Clara CA (US) for applied materials, inc., Yunil Cho of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, H01J37/244
CPC Code(s): H01J37/32926
Abstract: a method of monitoring a plasma-based process in a process chamber includes measuring a first temperature at a first location associated with a process chamber during a plasma-based process; and determining a value representative of a first radical species flux associated with the plasma-based process based on the first temperature. the method includes a trained machine learning model to determine if a value representative of a radical species flux satisfies a radical species flux drift threshold.
Inventor(s): Shanshan Yao of San Jose CA (US) for applied materials, inc., Bo Xie of San Jose CA (US) for applied materials, inc., Chi-I Lang of Cupertino CA (US) for applied materials, inc., Li-Qun Xia of Cupertino CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, C23C16/32, C23C16/40, C23C16/50
CPC Code(s): H01L21/02274
Abstract: exemplary semiconductor processing methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. the deposition precursors may include a silicon-oxygen-and-carbon-containing precursor. a substrate may be disposed within the processing region. the methods may include forming plasma effluents of the deposition precursors. the methods may include depositing a layer of silicon-oxygenâandâcarbon-containing material on the substrate. the layer of silicon-oxygenâandâcarbon-containing material may be characterized by a dielectric constant of less than or about 4.5. the layer of silicon-oxygenâandâcarbon-containing material may be characterized by a density of greater than or about 2.0 g/cm.
20250062122. Implant Hard Mask for Substrates_simplified_abstract_(applied materials, inc.)
Inventor(s): Jun FANG of Xi'an (CN) for applied materials, inc., Ludovico MEGALINI of Santa Clara CA (US) for applied materials, inc., Yi ZHENG of Sunnyvale CA (US) for applied materials, inc., Jang Seok OH of Santa Clara CA (US) for applied materials, inc., Feng shou WANG of Xiâan city (CN) for applied materials, inc.
IPC Code(s): H01L21/027, H01L21/02
CPC Code(s): H01L21/0273
Abstract: a method for forming an implant hard mask on a substrate provides a multi-layer hardmask resistant to high processing temperatures and ion energies. in some embodiments, the method may comprise depositing a screen layer of oxide material with a thickness of approximately 20 nm to approximately 100 nm, depositing a first layer of the implant hard mask of amorphous carbon with a second thickness of approximately 100 nm to approximately 3000 nm; depositing a second layer of the implant hard mask of oxide with a third thickness of approximately 100 nm to approximately 3000 nm; depositing a photoresist layer on the second layer of the implant hard mask, and patterning the photoresist layer to expose portions of the second layer of the implant hard mask, etching the second layer of the implant hard mask and then the first layer of the implant hard mask using a hard mask etch process to expose portions of the screen layer.
Inventor(s): SHASHANK SHARMA of Sunnyvale CA (US) for applied materials, inc., KAI B. NG of Santa Clara CA (US) for applied materials, inc., NORMAN TAM of Cupertino CA (US) for applied materials, inc., YUQI GUO of Sunnyvale CA (US) for applied materials, inc., ANDY LO of San jose CA (US) for applied materials, inc., HUIXIONG DAI of San jose CA (US) for applied materials, inc., KHOI PHAN of San jose CA (US) for applied materials, inc., CHIHAN HSU of Milpitas CA (US) for applied materials, inc., MADHUR SACHAN of Belmont CA (US) for applied materials, inc., NASRIN KAZEM of Santa Clara CA (US) for applied materials, inc., ZHENXING HAN of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/027, H01L21/308, H01L21/311, H01L21/3213
CPC Code(s): H01L21/0274
Abstract: embodiments disclosed herein include a method of thermal treatment or radical species treatment of a photoresist a metal-oxide photoresist. in an embodiment, a method of patterning a metal-oxide photoresist, such as a sn-based photoresist, includes depositing the metal-oxide photoresist over a substrate, exposing the metal-oxide photoresist with an extreme ultra-violet (euv) exposure to form exposed regions and non-exposed regions, developing the exposed metal-oxide photoresist, and performing a thermal treatment and/or a radical species treatment of the metal-oxide photoresist.
Inventor(s): Yin Wei LIM of Singapore (SG) for applied materials, inc., Guan Huei SEE of Singapore (SG) for applied materials, inc., Chang Bum YONG of Singapore (SG) for applied materials, inc., Prayudi LIANTO of Singapore (SG) for applied materials, inc., Arvind SUNDARRAJAN of Singapore (SG) for applied materials, inc., Cheng SUN of Singapore (SG) for applied materials, inc.
IPC Code(s): H01L21/3065, H01L23/00, H01L25/065
CPC Code(s): H01L21/3065
Abstract: embodiments of the disclosure include an apparatus and method of forming a backside profile in a semiconductor device that includes die-to-wafer bonding. the method generally includes removing a portion of a substrate layer included in a plurality of dies, the plurality of dies arranged on and bonded to an insulation layer included in a support structure, where the plurality of dies define a plurality of channels between adjacent dies, and forming a corner feature on a plurality of corners of the substrate layer adjacent to the plurality of channels. the use of a backside profile as described herein may mitigate the downstream process risks associated with trapped residue in the channels, and provide stress relief to the semiconductor device.
Inventor(s): Hanbyul Jin of San Jose CA (US) for applied materials, inc., Sangjun Park of Fremont CA (US) for applied materials, inc., Menghui Li of Mountain View CA (US) for applied materials, inc., Xiawan Yang of San Jose CA (US) for applied materials, inc., Sunil Srinivasan of Pleasanton CA (US) for applied materials, inc., Meishen Liu of Sunnyvale CA (US) for applied materials, inc., Andrew Butler of Boise ID (US) for applied materials, inc., Qian Fu of Pleasanton CA (US) for applied materials, inc.
IPC Code(s): H01L21/308, H01L21/02, H01L21/3065, H01L21/311
CPC Code(s): H01L21/308
Abstract: methods of semiconductor processing may include forming plasma effluents of a plurality of precursors (e.g., an etchant precursor, an oxygen-containing precursor, and a silicon-and-fluorine-containing precursor like silicon tetrafluoride). the plasma effluents may then contact a silicon-containing material and a mask material on a substrate in a processing region of a semiconductor processing chamber. the mask material may have one or more apertures therein that allow the plasma effluents access to the silicon-containing material. contacting the silicon-containing material and the mask material with the plasma effluents may cause (i) etching the silicon-containing material with the plasma effluents to form and/or deepen one or more features in the silicon-containing material and (ii) simultaneously etching the mask material and depositing a silicon-and-oxygen-containing material on the mask material with the plasma effluents.
Inventor(s): Deepak Patel of Karnataka (IN) for applied materials, inc., Pandu Maddherla of Karnataka (IN) for applied materials, inc., Sushant S. Koshti of Sunnyvale CA (US) for applied materials, inc., Jeffrey C. Hudgens of San Francisco CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, B33Y10/00, B33Y80/00, H01L21/68, H01L21/687
CPC Code(s): H01L21/67259
Abstract: a load lock including a substrate support device for supporting a substrate, and an indexer coupled to the substrate support device. the substrate support device may take measurements and acquire data to verify features of the supported substrate and an associated manufacturing system. substrate features that are measured include, substrate temperature, substrate warping, and a substrate presence, absence, or misplacement on the support device. system features that are measured include system vibrations and substrate transfer mechanism calibration data. the substrate support device sensors and communications circuits can be integrated into the substrate support device, through use of an additive manufacturing process in making the substrate support device.
Inventor(s): Adrian Rhee of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, G05B19/4155, G06N20/00
CPC Code(s): H01L21/67276
Abstract: a method includes identifying, by at least one processing device from a set of wafers, an idle wafer that is idle for a duration that exceeds a predefined threshold value, wherein each wafer of the set of wafers is associated with a respective start time of a set of start times, and initiating, by the at least one processing device, a computer simulation forecasting processing of the set of wafers using a wafer modification chamber and a wafer movement chamber based on a modified set of start times, wherein the computer simulation uses a machine learning model trained to perform a first manufacturing task using the wafer modification chamber and to perform a second manufacturing task using the wafer movement chamber, and wherein the modified set of start times is obtained by modifying at least one start time of the set of start times.
20250062145. Large Format Continuous Imaging System_simplified_abstract_(applied materials, inc.)
Inventor(s): Venkatakaushik VOLETI of San Jose CA (US) for applied materials, inc., Mehdi VAEZ-IRAVANI of Los Gatos CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, G06T7/00, G06T7/73
CPC Code(s): H01L21/67288
Abstract: a scanning inspection apparatus detects anomalies on surfaces of objects such as substrates, substrates with bonded chiplets, and carriers with singulated chiplets and the like. in some embodiments, the inspection apparatus includes a time delay integrated (tdi) linear sensor with an optical input and a data output where more than one optical assembly is positioned adjacent to each other with an optical output focused on a different segment of the tdi linear sensor and with an optical input positioned to receive a portion of a surface under examination. the apparatus may further include a platform with an upper surface for supporting an object with the surface under examination and with a motion assembly to move the platform and with a controller in communication with the motion assembly to move the platform in relation to the optical input of the optical assembly.
Inventor(s): Ge QU of Sunnyvale CA (US) for applied materials, inc., Zhiyuan WU of San Jose CA (US) for applied materials, inc., Jiajie CEN of Santa Clara CA (US) for applied materials, inc., Feng CHEN of San Jose CA (US) for applied materials, inc., Kevin KASHEFI of Dublin CA (US) for applied materials, inc., Chengyu LIU of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, H01L21/02
CPC Code(s): H01L21/76867
Abstract: a method of forming a metal interconnect in a semiconductor structure includes performing a barrier layer deposition process to deposit a barrier layer within an opening formed through a dielectric layer, performing a liner deposition process to deposit a liner layer on the barrier layer, performing a metal treatment process to implant metal dopants into a surface of the liner layer, and performing a gap fill process to form a metal interconnect on the metal treated surface of the liner layer within the opening.
Inventor(s): Nicholas A. Wiswell of Sunnyvale CA (US) for applied materials, inc., Benjamin Cherian of San Jose CA (US) for applied materials, inc., Haoquan Fang of Sunnyvale CA (US) for applied materials, inc., Jun Qian of Sunnyvale CA (US) for applied materials, inc., Thomas H. Osterheld of Mountain View CA (US) for applied materials, inc., Sohrab Pourmand of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/66, B24B37/005
CPC Code(s): H01L22/20
Abstract: disclosed herein is a chemical mechanical polishing apparatus, comprising a platen to support a polishing pad; a carrier head to hold a surface of a substrate against the polishing pad; a motor to generate relative motion between the platen and the carrier head so as to polish an overlying layer on the substrate; an in-situ acoustic monitoring system including an acoustic sensor that receives acoustic energy from the substrate and the polishing pad; and a controller configured to detect an abnormal acoustic event based on measurements from the in-situ acoustic monitoring system, and determine a type of anomaly based on signals measured by the in-situ acoustic monitoring system during the abnormal acoustic event.
Inventor(s): Zhijun CHEN of San Jose CA (US) for applied materials, inc., Fredrick FISHBURN of Aptos CA (US) for applied materials, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/03
Abstract: examples herein relate to three-dimensional (3d) dynamic random access memory (dram) and corresponding methods. in an example, a stacked semiconductor structure is provided, where the stacked semiconductor structure includes a plurality of unit stacks formed on a substrate. each unit stack has a semiconductor layer, a first dielectric layer, a first gate electrode, and a second dielectric layer of a capacitor portion. a lateral recess of the capacitor portion is open to a first opening through the unit stack. the method includes conformally depositing, in the lateral recess, a doped silicon layer on a lateral end of the semiconductor layer, performing a thermal annealing process after forming the doped silicon layer on the second lateral end. the method further includes forming a capacitor where the lateral recess was disposed, the capacitor contacting the doped silicon layer on the second lateral end of the semiconductor layer.
Inventor(s): Kyoung Ha KIM of Santa Clara CA (US) for applied materials, inc., Veeraraghavan S. BASKER of Schenectady NY (US) for applied materials, inc., Byeong Chan LEE of San Jose CA (US) for applied materials, inc., Andrew YEOH of Portland OR (US) for applied materials, inc.
IPC Code(s): H01L29/417, H01L21/283, H01L21/3065, H01L29/06, H01L29/423, H01L29/45, H01L29/775, H01L29/786
CPC Code(s): H01L29/4175
Abstract: a method of forming a portion of a gate-all-around field-effect transistor includes performing a selective deposition process to form selective cap layers at bottoms of contact trenches formed within portions of a substrate isolated by shallow trench isolations (stis), wherein the contact trenches each interface with an s/d epitaxial (epi) layer with an extension region, performing a substrate angled etch process to etch sidewalls of the contact trenches, enlarging top critical dimension (cd) of the contact trenches, performing a substrate selective removal plasma (srp) etch process to isotropically etch the substrate within the contact trenches, performing a recess fill process to fill the contact trenches with dielectric layers, performing an inter-layer dielectric (ild) recess process to partially remove the substrate between the dielectric layers within the contact trenches and form an ild recess, and performing a substrate isotropic etch process to partially remove the substrate within the ild recess.
Applied Materials, Inc. patent applications on February 20th, 2025
- Applied Materials, Inc.
- B23K26/0622
- CPC B23K26/0622
- Applied materials, inc.
- C23C14/24
- G01F11/28
- H01M4/02
- H01M4/04
- H01M4/38
- H01M10/052
- CPC C23C14/246
- F16K3/02
- CPC F16K3/0227
- F16K31/06
- B04C3/06
- F16K37/00
- CPC F16K31/0655
- G01N15/06
- H01J37/32
- CPC G01N15/0656
- G01N21/95
- G01N35/00
- CPC G01N21/9505
- G06T7/00
- G06V10/147
- CPC G06T7/0004
- H03H7/38
- CPC H01J37/32724
- H01J37/244
- CPC H01J37/32926
- H01L21/02
- C23C16/32
- C23C16/40
- C23C16/50
- CPC H01L21/02274
- H01L21/027
- CPC H01L21/0273
- H01L21/308
- H01L21/311
- H01L21/3213
- CPC H01L21/0274
- H01L21/3065
- H01L23/00
- H01L25/065
- CPC H01L21/3065
- CPC H01L21/308
- H01L21/67
- B33Y10/00
- B33Y80/00
- H01L21/68
- H01L21/687
- CPC H01L21/67259
- G05B19/4155
- G06N20/00
- CPC H01L21/67276
- G06T7/73
- CPC H01L21/67288
- H01L21/768
- CPC H01L21/76867
- H01L21/66
- B24B37/005
- CPC H01L22/20
- H10B12/00
- CPC H10B12/03
- H01L29/417
- H01L21/283
- H01L29/06
- H01L29/423
- H01L29/45
- H01L29/775
- H01L29/786
- CPC H01L29/4175