Applied Materials, Inc. patent applications on February 13th, 2025
Patent Applications by Applied Materials, Inc. on February 13th, 2025
Applied Materials, Inc.: 27 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01J37/32 (6), H01L21/02 (4), H01L21/768 (4), G03F7/00 (3), C23C16/455 (3) H01L21/02274 (2), C23C12/00 (1), H01J37/32816 (1), H01L21/823807 (1), H01L21/76889 (1)
With keywords such as: substrate, layer, include, material, chamber, processing, surface, methods, support, and precursor in patent application abstracts.
Patent Applications by Applied Materials, Inc.
Inventor(s): Chandan Das of Singapore (SG) for applied materials, inc., Bencherki Mebarki of Santa Clara CA (US) for applied materials, inc., Jiecong Tang of Singapore (SG) for applied materials, inc., Mohammed Mahdi Tavakoli of Sunnyvale CA (US) for applied materials, inc., John Sudijono of Singapore (SG) for applied materials, inc., Joung Joo Lee of San Jose CA (US) for applied materials, inc.
IPC Code(s): C23C12/00, C23C16/40, C23C16/455, C23C16/56
CPC Code(s): C23C12/00
Abstract: transition metal dichalcogenide (tmdc) films and methods for conformally depositing tmdc films on a substrate surface are described. the substrate surface may have one or more features formed therein, one or more layers formed thereon, and combinations thereof. the substrate surface is exposed to a transition metal precursor and an oxidant to form a transition metal oxide film in a first phase. the transition metal oxide film is exposed to a chalcogenide precursor to convert the transition metal oxide film to the tmdc film in a second phase.
Inventor(s): Shinichi OKI of Chiba-Ken (JP) for applied materials, inc., Yoshinobu MORI of Tokyo (JP) for applied materials, inc., Yuji AOKI of Yokohama-Shi Kanagawa-Ken (JP) for applied materials, inc.
IPC Code(s): C23C16/44, C23C16/458, C23C16/46, C30B25/10, C30B25/12, H01L21/687
CPC Code(s): C23C16/4408
Abstract: a pre-heat ring and a process chamber having the same are described herein. in one example, a process chamber for film deposition comprises a chamber volume, a substrate support disposed in the chamber volume, the substrate support having a radially outward surface, and a pre-heat ring surrounding the substrate support. the pre-heat ring comprises a tapered wall facing the radially outward surface. the tapered wall narrows towards a top surface of the pre-heat ring and towards the substrate support.
Inventor(s): Paul R. McHugh of Kalispell MT (US) for applied materials, inc., Charles Sharbono of Kalispell MT (US) for applied materials, inc., Jing Xu of Kalispell MT (US) for applied materials, inc., John L. Klocke of Kalispell MT (US) for applied materials, inc., Sam K. Lee of Kalispell MT (US) for applied materials, inc., Keith Edward Ypma of Kalispell MT (US) for applied materials, inc.
IPC Code(s): C25D5/18, C25D5/02, C25D7/12, C25D17/00, C25D21/12, G06F30/20, H01L21/768
CPC Code(s): C25D5/18
Abstract: a method of plating substrates may include placing a substrate in a plating chamber comprising a liquid, and applying a current to the liquid in the plating chamber to deposit a metal on exposed portions of the substrate, where the current may include alternating cycles of a forward plating current and a reverse deplating current. to determine the current characteristics, a model of a substrate may be simulated during the plating process to generate data points that relate characteristics of the plating process and a pattern on the substrate to a range nonuniformity of material formed on the substrate during the plating process. using information from the data points, values for the forward and reverse currents may be derived and provided to the plating chamber to execute the plating process.
Inventor(s): Gautam PISHARODY of Newark CA (US) for applied materials, inc., Parth SWAROOP of Bangalore (IN) for applied materials, inc., Xiaoxiong YUAN of San Jose CA (US) for applied materials, inc., Paneendra Prakash BHAT of Santa Clara CA (US) for applied materials, inc., Qiwei LIANG of Fremont CA (US) for applied materials, inc., Dmitry LUBOMIRSKY of Cupertino CA (US) for applied materials, inc., Adib KHAN of Santa Clara CA (US) for applied materials, inc., Douglas A. BUCHBERGER, Jr. of Livermore CA (US) for applied materials, inc.
IPC Code(s): C30B35/00, C30B25/02
CPC Code(s): C30B35/00
Abstract: disclosed herein are a showerhead and a deposition chamber containing the showerhead. the showerhead includes a first delivery network for a first precursor that comprises a first manifold connected with a first distribution system comprising a plurality of first distribution channels concentrically disposed around an axis, and a second delivery network for a second precursor that comprises a second manifold connected with a second distributions system comprising a plurality of second distribution channels concentrically disposed around the axis. the first delivery network and the second delivery network are isolated from each other within the showerhead.
Inventor(s): Helinda Nominada of San Jose CA (US) for applied materials, inc., Harvey You of San Jose CA (US) for applied materials, inc., Han Nguyen of San Jose CA (US) for applied materials, inc., Tae Kyung Won of San Jose CA (US) for applied materials, inc., Seong Ho Yoo of San Ramon CA (US) for applied materials, inc., Soo Young Choi of Fremont CA (US) for applied materials, inc.
IPC Code(s): G02B1/14
CPC Code(s): G02B1/14
Abstract: exemplary flexible coverlenses and the methods of making them are described. the methods may include exposing a surface of a substrate layer to a surface treatment plasma to form a treated surface of the substrate layer. a silicon-containing adhesion layer may be deposited on the treated surface of the substrate layer. a silane-containing adhesion promoter may be incorporated on the silicon-containing adhesion layer. the method may also include forming a hardcoat layer on the silicon-containing adhesion layer, where the silane-containing adhesion promoter is bonded to both the hardcoat layer and the silicon-containing adhesion layer. the exemplary flexible coverlenses made by the present methods are less susceptable to folding fatigue along a bending or folding axis of the coverlens.
Inventor(s): Yingnan LIU of Santa Clara CA (US) for applied materials, inc., Samarth BHARGAVA of Saratoga CA (US) for applied materials, inc., Kevin MESSER of Mountain View CA (US) for applied materials, inc., Evan WANG of Palo Alto CA (US) for applied materials, inc., David Alexander SELL of Santa Clara CA (US) for applied materials, inc., Simon LORENZO of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): F21V8/00, G02B27/00
CPC Code(s): G02B6/0016
Abstract: embodiments of the present disclosure include apparatus and methods for optical devices. in one embodiment, a method for forming an optical device generally includes disposing a first material device layer on a substrate, patterning a portion of the first material device layer to form a first plurality of device structures in the first material device layer, disposing a second material device layer on an un-patterned portion of the first device material layer, and patterning the second material device layer to form a second plurality of device structures disposed on the first material device layer.
Inventor(s): Yongan XU of Santa Clara CA (US) for applied materials, inc., Jinxin FU of Fremont CA (US) for applied materials, inc., Jhenghan YANG of San Jose CA (US) for applied materials, inc., Ludovic GODET of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): G03F7/00, G02B6/122, G02B6/136
CPC Code(s): G03F7/0007
Abstract: the present disclosure generally relates to methods of forming optical devices comprising nanostructures disposed on transparent substrates. a first process of forming the nanostructures comprises depositing a first layer of a first material on a glass substrate, forming one or more trenches in the first layer, and depositing a second layer of a second material in the one or more holes to trenches a first alternating layer of alternating first portions of the first material and second portions of the second material. the first process is repeated one or more times to form additional alternating layers over the first alternating layer. each first portion of each alternating layer is disposed in contact with and offset a distance from an adjacent first portion in adjacent alternating layers. a second process comprises removing either the first or the second portions from each alternating layer to form the plurality of nanostructures.
Inventor(s): MADHUR SACHAN of Belmont CA (US) for applied materials, inc., BO XIE of San Jose CA (US) for applied materials, inc., LAKMAL CHARIDU KALUTARAGE of San Jose CA (US) for applied materials, inc., ZHENXING HAN of Sunnyvale CA (US) for applied materials, inc., TZU SHUN YANG of Milpitas CA (US) for applied materials, inc., LI-QUN XIA of Cupertino CA (US) for applied materials, inc.
IPC Code(s): G03F7/004, G03F7/075, G03F7/16, G03F7/20
CPC Code(s): G03F7/0043
Abstract: embodiments disclosed herein include a method of post development treatment of a metal-oxide photoresist. in an embodiment, a method includes depositing a metal-oxide photoresist over a substrate, exposing the metal-oxide photoresist with an extreme ultra-violet (euv) exposure to form exposed regions and unexposed regions, developing the exposed metal-oxide photoresist, and performing a surface treatment of the developed metal-oxide photoresist to form a coating on the developed metal-oxide photoresist.
Inventor(s): Yangyang SUN of San Jose CA (US) for applied materials, inc., Jinxin FU of Fremont CA (US) for applied materials, inc., Sihui HE of Santa Clara CA (US) for applied materials, inc., Ludovic GODET of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/706849
Abstract: embodiments described herein provide an asymmetric optical metrology system for evaluating and inspecting the performance of optical devices, such as augmented reality (ar) waveguide combiners. the system utilizes an asymmetric optical configuration and fly-eye illumination to enhance the detection limit of image sharpness and the accuracy of luminance uniformity. by employing different lenses with various focal lengths, the system increases the sampling rate in the angular space, addressing the challenges of form factor limitations and pixel density inherent in conventional metrology tools. embodiments described herein offer improved contrast and sharp image details, as well as a compact design, making it suitable for the development, optimization, and quality control of optical devices, such as ar waveguide combiners.
Inventor(s): Assaf Kidron of Cupertino CA (US) for applied materials, inc., Rudolf Brunner of Menlo Park CA (US) for applied materials, inc., Davidi Kalir of Hod Hashron (IL) for applied materials, inc., Timothy Thomas of Portland OR (US) for applied materials, inc., Anilkumar Borkar of Bangalore (IN) for applied materials, inc., Jiawei Shi of Union City CA (US) for applied materials, inc.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/70833
Abstract: embodiments of the disclosure relate to digital lithography systems and components thereof. digital lithography systems may include a rotation assembly for an exposure unit, including a kinematic socket configured to support the exposure unit, the kinematic socket having a socket seat and a sphere received in the socket seat, wherein the socket seat is configured to support a load of the exposure unit during translational movement and the sphere is a pivot point for tip and tilt movement; and a motor configured to rotate the one or more exposure unit via the kinematic socket. the rotation assembly may provide a point of contact for the exposure unit together with two additional points of contact that stabilize movement of the exposure unit. also disclosed are methods of preparation and use of such systems and components.
Inventor(s): Preetham Prahallada Rao of Morgan Hill CA (US) for applied materials, inc., Prashanth Kothnur of San Jose CA (US) for applied materials, inc.
IPC Code(s): G06F30/27, G06F18/214, G06F111/06, G06N20/20, H01L21/67
CPC Code(s): G06F30/27
Abstract: a method includes measuring a subset of property values within a manufacturing chamber during a process performed on a substrate within the manufacturing chamber. the method further includes determining property values in the manufacturing chamber at locations removed from the locations the measurements are taken. the method further includes performing a corrective action based on the determined properties.
Inventor(s): Jinxin FU of Fremont CA (US) for applied materials, inc., Yangyang SUN of San Jose CA (US) for applied materials, inc., Ludovic GODET of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): G06T7/521, G06T1/00
CPC Code(s): G06T7/521
Abstract: embodiments herein provide for a method of determining an optical device modulation transfer function (mtf). the method described herein includes projecting a first instance of an image from a light engine to a detector. the first instance of the image is analyzed to determine a first function. a first fast fourier transform (fft) or a first mtf of the first function is obtained. the method further includes projecting a second instance of the image from the light engine to detector via one or more optical devices. the second instance of the image is analyzed to determine a second function. a second fft or a second mtf is obtained of the second function. an optical device mtf of the one or more optical devices is determined by comparing the first fft and the second fft or by comparing the first mtf and the second mtf.
20250054722. COOLED SPUTTERING TARGET FOR ION SOURCE_simplified_abstract_(applied materials, inc.)
Inventor(s): Ori Noked of Brookline MA (US) for applied materials, inc.
IPC Code(s): H01J37/08, H01J37/244, H01J37/317
CPC Code(s): H01J37/08
Abstract: an ion source with a target holder for holding a solid dopant material is disclosed. the target holder is mounted to a shaft, which may be in communication with an actuator, which allows the solid dopant material to be inserted and retracted from the arc chamber. the shaft and/or the target holder is actively cooled such that the solid dopant material remains below its melting point. in this way, the solid dopant material may be inserted into the arc chamber without any melting. the cooling mechanisms used may include gas cooling, liquid cooling, thermoelectric cooling or other cooling techniques.
Inventor(s): Karthik ELUMALAI of Singapore (SG) for applied materials, inc., Ananthkrishna JUPUDI of Singapore (SG) for applied materials, inc., Arunkumar TATTI of Bangalore (IN) for applied materials, inc., Cheng SUN of Singapore (SG) for applied materials, inc., Ye LIU of Singapore (SG) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32724
Abstract: embodiments of substrate supports having electrostatic chucks (escs) for use in substrate process chambers are provided herein. in some embodiments, a substrate support includes: an electrostatic chuck (esc) having a top surface and a plurality of mesas extending upward from the top surface, wherein an upper surface of the plurality of mesas define a substrate support surface, wherein a total surface area of the substrate support surface is about 18 to about 40 percent a total surface area of the upper surface, and wherein the esc includes a plurality of backside gas openings extending through the esc; and one or more chucking electrodes disposed in the esc.
Inventor(s): Qiwei Liang of Fremont CA (US) for applied materials, inc., Srinivas D. Nemani of Sunnyvale CA (US) for applied materials, inc., Keith Tatseun Wong of Mountain View CA (US) for applied materials, inc., Antony K. Jan of Mountain View CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, C23C16/04, H01L21/027, H01L21/32
CPC Code(s): H01J37/32816
Abstract: a method includes flowing an evaporated low vapor pressure organic molecule (om) into a processing chamber including a substrate. the method further includes depositing, in the processing chamber, the low vapor pressure om onto at least a portion of the substrate at a first temperature and a first pressure to form a self-assembled monolayer (sam) on at least the portion of the substrate. the method further includes annealing, in the processing chamber, the sam on at least the portion of the substrate at a second temperature and a second pressure. the second pressure is greater than the first pressure and the second temperature is greater than the first temperature.
Inventor(s): Guangyan Zhong of Sunnyvale CA (US) for applied materials, inc., Jongbeom Seo of San Jose CA (US) for applied materials, inc., Eswaranand Venkatasubramanian of Santa Clara CA (US) for applied materials, inc., Abhijit Basu Mallick of Fremont CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, C23C16/02, C23C16/50, H01J37/32, H01L21/285
CPC Code(s): H01L21/02274
Abstract: exemplary methods of semiconductor processing may include providing a treatment precursor to a processing region of a semiconductor processing chamber. a substrate may be disposed within the processing region. the methods may include contacting a surface of the substrate with the treatment precursor. the methods may include providing deposition precursors to the processing region. the deposition precursors may include a metal-containing precursor. the methods may include forming plasma effluents of the deposition precursors. the methods may include contacting the substrate with the plasma effluents of the deposition precursors. the contacting may deposit a metal-containing hardmask on the substrate.
Inventor(s): Kent Zhao of San Francisco CA (US) for applied materials, inc., Rui Lu of Santa Clara CA (US) for applied materials, inc., Bo Xie of San Jose CA (US) for applied materials, inc., Shanshan Yao of San Jose CA (US) for applied materials, inc., Xiaobo Li of San Jose CA (US) for applied materials, inc., Chi-I Lang of Cupertino CA (US) for applied materials, inc., Li-Qun Xia of Cupertino CA (US) for applied materials, inc., Shankar Venkataraman of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, C23C16/40, C23C16/505, C23C16/56, H01J37/32
CPC Code(s): H01L21/02274
Abstract: exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. a substrate may be disposed within the processing region of the semiconductor processing chamber. the methods may include forming a plasma of the silicon-containing precursor in the processing region. the plasma may be at least partially formed by a pulsing rf power operating at less than or about 2,000 w. the methods may include forming a layer of silicon-containing material on the substrate. the layer of silicon-containing material may be characterized by a dielectric constant less than or about 3.0.
Inventor(s): Pradeep Kumar Subrahmanyan of San Jose CA (US) for applied materials, inc., Wonjae Lee of Fremont CA (US) for applied materials, inc., Ramkumar Karur Shanmugam of Cupertino CA (US) for applied materials, inc., Olga Kucher of Santa Clara CA (US) for applied materials, inc., Adaeze Osonkie of Santa Clara CA (US) for applied materials, inc., San-Kuei Lin of Los Gatos CA (US) for applied materials, inc.
IPC Code(s): H01L21/027, H01L21/02, H01L21/66
CPC Code(s): H01L21/0274
Abstract: disclosed systems and techniques are directed to improvement of semiconductor manufacturing. in one disclosed embodiment, the disclosed systems and techniques include depositing one or more films on a front surface of a substrate, forming a stress compensation layer (scl) on the one or more deposited films, the scl causing stress in the substrate to be changed, subjecting the scl to a stress-mitigation beam to reduce deformation of the substrate, and adding one or more features to at least one of the one or more deposited films.
Inventor(s): Qihao ZHU of Sunnyvale CA (US) for applied materials, inc., Shumao ZHANG of San Jose CA (US) for applied materials, inc., Weifeng YE of San Jose CA (US) for applied materials, inc., Yiyang WAN of Sunnyvale CA (US) for applied materials, inc., Gary HOW of Santa Clara CA (US) for applied materials, inc., Jianqiu GUO of San Jose CA (US) for applied materials, inc., Dong WANG of Zhuhai (CN) for applied materials, inc., Shihchung CHEN of Cupertino CA (US) for applied materials, inc., Liqi WU of San Jose CA (US) for applied materials, inc., Jiang LU of Milpitas CA (US) for applied materials, inc.
IPC Code(s): H01L21/285, C23C16/02, C23C16/04, C23C16/14, C23C16/42, C23C16/455, C23C16/50, C23C16/52, H01J37/32, H01L21/02, H01L21/768
CPC Code(s): H01L21/28518
Abstract: embodiments include a method of forming a contact structure on a semiconductor substrate. the method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.
Inventor(s): Jiajing Li of San Jose CA (US) for applied materials, inc., Mengjie Lyu of Santa Clara CA (US) for applied materials, inc., Menghui Li of Mountain View CA (US) for applied materials, inc., Xiawan Yang of San Jose CA (US) for applied materials, inc., Olivier P. Joubert of Meylan (FR) for applied materials, inc., Susumu Shinohara of Yokohama-Shi (JP) for applied materials, inc., Qian Fu of Pleasanton CA (US) for applied materials, inc.
IPC Code(s): H01L21/3065, H01L21/308
CPC Code(s): H01L21/3065
Abstract: exemplary semiconductor processing methods may include providing an oxygen-containing precursor and a sulfur-containing precursor to a processing region of a semiconductor processing chamber. a substrate may be housed in the processing region. a layer of carbon-containing material may be disposed on the substrate. the methods may include forming plasma effluents of the oxygen-containing precursor and the sulfur-containing precursor. the methods may include contacting the substrate with the plasma effluents of the oxygen-containing precursor and the sulfur-containing precursor. the contacting may etch a feature in the layer of carbon-containing material. a chamber operating temperature may be maintained at less than or about 0� c.
Inventor(s): Jiajing Li of San Jose CA (US) for applied materials, inc., Mengjie Lyu of Santa Clara CA (US) for applied materials, inc., Menghui Li of Mountain View CA (US) for applied materials, inc., Xiawan Yang of San Jose CA (US) for applied materials, inc., Olivier P. Joubert of Meylan (FR) for applied materials, inc., Susumu Shinohara of Yokohama-Shi (JP) for applied materials, inc., Qian Fu of Pleasanton CA (US) for applied materials, inc.
IPC Code(s): H01L21/311
CPC Code(s): H01L21/31116
Abstract: exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. a substrate may be housed in the processing region. a layer of oxygen-containing material may be disposed on the substrate. the methods may include forming plasma effluents of the fluorine-containing precursor and the carbon-containing precursor. the methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor and the carbon-containing precursor. the contacting may etch a feature in the layer of oxygen-containing material. a semiconductor processing chamber operating temperature may be maintained at less than or about 0� c. during the semiconductor processing method.
Inventor(s): John C. Menk of Round Rock TX (US) for applied materials, inc., Rachel Sara Stolzman of Saratoga CA (US) for applied materials, inc., Douglas R. McAllister of San Ramon CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, G06K19/07, H01L21/677
CPC Code(s): H01L21/67196
Abstract: an enclosure system includes a plurality of walls configured to at least partially enclose an interior volume. the enclosure system further includes a radio-frequency identification (rfid) holder configured to secure an rfid component and further configured to seal an opening formed in at least one of the plurality of walls. the enclosure system further includes a plurality of shelves configured to support a plurality of objects within the interior volume.
Inventor(s): Katherine Woo of Santa Clara CA (US) for applied materials, inc., Paul L. Brillhart of Pleasanton CA (US) for applied materials, inc., Jian Li of Fremont CA (US) for applied materials, inc., Shinnosuke Kawaguchi of Adachi-Ku (JP) for applied materials, inc., David W. Groechel of Synnyvale CA (US) for applied materials, inc., Dorothea Buechel-Rimmel of Synnyvale CA (US) for applied materials, inc., Juan Carlos Rocha-Alvarez of San Carlos CA (US) for applied materials, inc., Paul E. Fisher of Los Altos CA (US) for applied materials, inc., Chidambara A. Ramalingam of Fremont CA (US) for applied materials, inc., Joseph J. Farah of Hollister CA (US) for applied materials, inc.
IPC Code(s): H01L21/68, G01L9/08, H01J37/32, H01L21/67, H01L21/683, H04Q9/00
CPC Code(s): H01L21/68
Abstract: exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. the chamber body may define an interior volume. the systems may include a substrate support extending through the base of the chamber body. the substrate support may be configured to support a substrate within the interior volume. the systems may include a faceplate positioned within the interior volume of the chamber body. the faceplate may define a plurality of apertures through the faceplate. the systems may include a leveling apparatus seated on the substrate support. the leveling apparatus may include a plurality of piezoelectric pressure sensors.
Inventor(s): Sanjeev Baluja of Campbell CA (US) for applied materials, inc., Tejas Ulavi of Fremont CA (US) for applied materials, inc., Eric J. Hoffmann of San Francisco CA (US) for applied materials, inc., Ashutosh Agarwal of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/687, C23C16/455, C23C16/458
CPC Code(s): H01L21/68742
Abstract: apparatus and methods for loading and unloading substrates from a spatial processing chamber are described. a support assembly has a rotatable center base and support arms extending therefrom. a support shaft is at the outer end of the support arms and a substrate support is on the support shaft. primary lift pins are positioned within openings in the substrate support. secondary lift pins are positioned within openings in the support arms and are aligned with the primary lift pins. an actuation plate within the processing volume causes, upon movement of the support assembly, the primary lift pins to elevate through contact with the secondary lift pins.
Inventor(s): Qihao ZHU of Sunnyvale CA (US) for applied materials, inc., Shumao ZHANG of San Jose CA (US) for applied materials, inc., Weifeng YE of San Jose CA (US) for applied materials, inc., Yiyang WAN of Sunnyvale CA (US) for applied materials, inc., Gary HOW of Santa Clara CA (US) for applied materials, inc., Jianqiu GUO of San Jose CA (US) for applied materials, inc., Dong WANG of Zhuhai (CN) for applied materials, inc., Shihchung CHEN of Cupertino CA (US) for applied materials, inc., Liqi WU of San Jose CA (US) for applied materials, inc., Jiang LU of Milpitas CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, H01L23/532, H01L23/535
CPC Code(s): H01L21/76889
Abstract: embodiments include a method of forming a contact structure on a semiconductor substrate. the method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.
Inventor(s): San-Kuei Lin of Los Gatos CA (US) for applied materials, inc., Pradeep K. Subrahmanyan of Los Gatos CA (US) for applied materials, inc.
IPC Code(s): H01L21/8238, H01L21/768, H01L29/15, H01L29/66
CPC Code(s): H01L21/823807
Abstract: embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. in some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.
Inventor(s): Peiwen LIU of Fremont CA (US) for applied materials, inc., Uma SRIDHAR of Sunnyvale CA (US) for applied materials, inc., Hyunsung BANG of Sunnyvale CA (US) for applied materials, inc., Kai DING of Cupertino CA (US) for applied materials, inc., Jeffrey L. FRANKLIN of Albuquerque NM (US) for applied materials, inc., Mingwei ZHU of San Jose CA (US) for applied materials, inc., Hou T. NG of Campbell CA (US) for applied materials, inc., Nag B. PATIBANDLA of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L33/00, H01L25/075
CPC Code(s): H01L33/005
Abstract: the present disclosure provides devices and methods for repairing dice during micro-led display fabrication. the devices include a backplane. the backplane has a plurality of backplane electrodes. each backplane electrode includes a first material. a plurality of micro-leds having a plurality of micro-led electrodes is included in the device. each micro-led electrode includes a second material. each micro-led electrode is bonded to each backplane electrode with an alloy of the first material and the second material therebetween. at least one backplane electrode is bonded to the micro-led electrode via a repair material. the device includes a plurality of subpixel isolation (si) structures formed over the backplane. the si structures define wells of sub-pixels. each well includes a respective micro-led between adjacent si structures. the sub-pixels have a color conversion material disposed in the wells.
Applied Materials, Inc. patent applications on February 13th, 2025
- Applied Materials, Inc.
- C23C12/00
- C23C16/40
- C23C16/455
- C23C16/56
- CPC C23C12/00
- Applied materials, inc.
- C23C16/44
- C23C16/458
- C23C16/46
- C30B25/10
- C30B25/12
- H01L21/687
- CPC C23C16/4408
- C25D5/18
- C25D5/02
- C25D7/12
- C25D17/00
- C25D21/12
- G06F30/20
- H01L21/768
- CPC C25D5/18
- C30B35/00
- C30B25/02
- CPC C30B35/00
- G02B1/14
- CPC G02B1/14
- F21V8/00
- G02B27/00
- CPC G02B6/0016
- G03F7/00
- G02B6/122
- G02B6/136
- CPC G03F7/0007
- G03F7/004
- G03F7/075
- G03F7/16
- G03F7/20
- CPC G03F7/0043
- CPC G03F7/706849
- CPC G03F7/70833
- G06F30/27
- G06F18/214
- G06F111/06
- G06N20/20
- H01L21/67
- CPC G06F30/27
- G06T7/521
- G06T1/00
- CPC G06T7/521
- H01J37/08
- H01J37/244
- H01J37/317
- CPC H01J37/08
- H01J37/32
- CPC H01J37/32724
- C23C16/04
- H01L21/027
- H01L21/32
- CPC H01J37/32816
- H01L21/02
- C23C16/02
- C23C16/50
- H01L21/285
- CPC H01L21/02274
- C23C16/505
- H01L21/66
- CPC H01L21/0274
- C23C16/14
- C23C16/42
- C23C16/52
- CPC H01L21/28518
- H01L21/3065
- H01L21/308
- CPC H01L21/3065
- H01L21/311
- CPC H01L21/31116
- G06K19/07
- H01L21/677
- CPC H01L21/67196
- H01L21/68
- G01L9/08
- H01L21/683
- H04Q9/00
- CPC H01L21/68
- CPC H01L21/68742
- H01L23/532
- H01L23/535
- CPC H01L21/76889
- H01L21/8238
- H01L29/15
- H01L29/66
- CPC H01L21/823807
- H01L33/00
- H01L25/075
- CPC H01L33/005