Applied Materials, Inc. patent applications on April 3rd, 2025
Patent Applications by Applied Materials, Inc. on April 3rd, 2025
Applied Materials, Inc.: 25 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01L21/02 (6), H01J37/32 (5), H01L21/3065 (4), H01L21/67 (3), B24B37/005 (2) H01L21/3065 (3), B24B37/005 (2), H01L21/6833 (2), H01L21/0337 (1), H10D64/021 (1)
With keywords such as: layer, substrate, processing, include, precursor, methods, material, surface, chamber, and region in patent application abstracts.
Patent Applications by Applied Materials, Inc.
Inventor(s): Andrew J. Nagengast of Sunnyvale CA US for applied materials, inc., Jeonghoon Oh of Saratoga CA US for applied materials, inc., Kuen-Hsiang Chen of Sunnyvale CA US for applied materials, inc., Steven M. Zuniga of Soquel CA US for applied materials, inc., Takashi Fujikawa of San Jose CA US for applied materials, inc., Jay Gurusamy of Santa Clara CA US for applied materials, inc., Ekaterina A. Mikhaylichenko of San Jose CA US for applied materials, inc., Eric Lau of Santa Clara CA US for applied materials, inc., Huanbo Zhang of San Jose CA US for applied materials, inc., Welarumage Ravin Fernando of Santa Clara CA US for applied materials, inc.
IPC Code(s): B24B37/005, B24B37/04, B24B37/24, B24B49/16
CPC Code(s): B24B37/005
Abstract: chemical mechanical polishing system and method include a substrate is loaded into a carrier head having a housing having an upper carrier body and a lower carrier body, and a membrane assembly beneath the lower carrier body. a space between the lower carrier body and the membrane assembly defines a pressurizable chamber, a distance from a sensor in the lower carrier body to the membrane assembly is measured, and pressure in the pressurizable chamber is controlled based on the measured distances to maintain a consistent total downforce on the membrane assembly as the distance between the sensor and the membrane assembly changes.
Inventor(s): Nojan Motamedi of Sunnyvale CA US for applied materials, inc., Dominic J. Benvegnu of La Honda CA US for applied materials, inc., Boguslaw A. Swedek of Morgan Hill CA US for applied materials, inc., Harry Q. Lee of Los Altos CA US for applied materials, inc., Steven M. Zuniga of Soquel CA US for applied materials, inc., Justin Ho Kuen Wong of Pleasanton CA US for applied materials, inc.
IPC Code(s): B24B37/005, B24B49/12
CPC Code(s): B24B37/005
Abstract: a notch finding station includes a sensor to generate a signal that depends on an proportion of a sensing region of the sensor that is covered by the substrate, and a controller. the controller is configured to cause an actuator to position a carrier head relative to the sensor such that the sensing region of the sensor is at an edge of the substrate, cause the motor to generate rotational motion such that the sensing region of the sensor scans along a circumference of the substrate, and detect an angular position of a notch in the edge of the substrate based on a signal from the sensor, including compensating for a sinusoidal component of the signal resulting from an offset of the center of the substrate from the axis of rotation.
Inventor(s): Haosheng Wu of San Jose CA US for applied materials, inc., Hari Soundararajan of Sunnyvale CA US for applied materials, inc., Yen-Chu Yang of Santa Clara CA US for applied materials, inc., Jianshe Tang of San Jose CA US for applied materials, inc., Shou-Sung Chang of Mountain View CA US for applied materials, inc., Shih-Haur Shen of Sunnyvale CA US for applied materials, inc., Taketo Sekine of Cupertino CA US for applied materials, inc.
IPC Code(s): B24B37/015, B24B37/10, B24B49/02, B24B49/04, B24B49/14, B24B55/02, B24B57/02
CPC Code(s): B24B37/015
Abstract: a chemical mechanical polishing system includes a support to hold a polishing pad, a carrier head to hold a substrate against the polishing pad during a polishing process, an in-situ monitoring system configured to generate a signal indicative of an amount of material on the substrate, a temperature control system to control a temperature of the polishing process, and a controller coupled to the in-situ monitoring system and the temperature control system. the controller is configured to cause the temperature control system to vary the temperature of the polishing process in response to the signal.
Inventor(s): Huanbo Zhang of San Jose CA US for applied materials, inc., Ekaterina A. Mikhaylichenko of San Jose CA US for applied materials, inc., Jeonghoon Oh of Saratoga CA US for applied materials, inc., Andrew Nagengast of Sunnyvale CA US for applied materials, inc., Erik S. Rondum of San Ramon CA US for applied materials, inc., Brian J. Brown of Palo Alto CA US for applied materials, inc., Zhize Zhu of San Jose CA US for applied materials, inc.
IPC Code(s): B24B37/10, B24B37/26, B24B57/02
CPC Code(s): B24B37/107
Abstract: a chemical mechanical polishing (cmp) process may generally apply more pressure around a periphery of the polishing pad than at the center of the polishing pad. this may cause uneven material removal as the substrate moves along the surface of the polishing pad. therefore, the polishing pad may include one or more recesses around a periphery of the polishing pad to relieve pressure on the substrate. the one or more recesses may be connected to channels that extend radially outward from the recesses to the edge of the polishing pad. the recesses may collect polishing slurry during the cmp process and direct the slurry into the channels. the channels may then expel the collected polishing slurry off of the polishing pad to clear the recesses.
Inventor(s): Andrew J. Nagengast of Sunnyvale CA US for applied materials, inc., Jeonghoon Oh of Saratoga CA US for applied materials, inc., Kuen-Hsiang Chen of Sunnyvale CA US for applied materials, inc., Steven M. Zuniga of Soquel CA US for applied materials, inc., Takashi Fujikawa of San Jose CA US for applied materials, inc., Jay Gurusamy of Santa Clara CA US for applied materials, inc., Ekaterina A. Mikhaylichenko of San Jose CA US for applied materials, inc., Eric L. Lau of Santa Clara CA US for applied materials, inc., Huanbo Zhang of San Jose CA US for applied materials, inc., Welarumage Ravin Fernando of Santa Clara CA US for applied materials, inc.
IPC Code(s): B24B37/32
CPC Code(s): B24B37/32
Abstract: a carrier head for chemical mechanical polishing includes a housing for attachment to a drive shaft, a membrane assembly arranged beneath the lower carrier body, and a flexure. the membrane assembly includes a membrane support and a flexible membrane secured to the membrane support to defining a plurality of pressurizable lower chambers, with the flexible membrane having a lower surface that provides a substrate mounting surface. a flexible seal forms a pressurizable upper chamber between the housing and the membrane support. the flexure connects the membrane support to the housing, and the flexure extends through the pressurizable upper chamber.
Inventor(s): Sebastian FRANKE of Hanau DE for applied materials, inc., Daniel STOCK of Gießen DE for applied materials, inc., Tobias STOLLEY of Oberursel DE for applied materials, inc.
IPC Code(s): C23C14/54, C23C14/14, C23C14/24, G01B17/02
CPC Code(s): C23C14/54
Abstract: a calibration assembly for a lithium deposition process is described. the calibration assembly includes a carrier, and a piezoelectric resonator coupled to the carrier. the calibration assembly is configured for being processed in the lithium deposition process. the lithium deposition process includes a passivation. the piezoelectric resonator is configured for being electrically connected to a driver for determining a resonant frequency of the piezoelectric resonator. the resonant frequency is indicative of a thickness of a lithium film deposited on the piezoelectric resonator in the lithium deposition process. a change of the resonant frequency over time is indicative of the passivation of the lithium film.
Inventor(s): Sock Hoon LIM of Singapore SG for applied materials, inc., Ramie MADEJA of Singapore SG for applied materials, inc., Wee Teng FAN of Singapore SG for applied materials, inc.
IPC Code(s): G01B5/14, B05C21/00, B25J9/16
CPC Code(s): G01B5/14
Abstract: methods and apparatus for verifying alignment between an opaque shadow ring and a substrate are provided. in some embodiments, the apparatus includes a tool comprising: a transparent ring having an inner edge defining a central opening and an outer edge and having a top side and a bottom side; a gauge mark on or in the transparent ring spaced between the inner edge and the outer edge, the gauge mark extending around the inner edge; and a pin extending from the bottom side of the transparent ring and located between the gauge mark and the outer edge.
Inventor(s): Richard Allen SPRENKLE of South Hamilton MA US for applied materials, inc.
IPC Code(s): H01J37/317, H01J37/304
CPC Code(s): H01J37/3171
Abstract: techniques for inverting implanter process model for parameter generation are described. a method comprises receiving a set of process parameters and associated values for an ion implanter by an inverted control model, the inverted control model comprising an artificial neural network (ann), predicting a set of control parameters and associated values for the ion implanter based on the set of process parameters and associated values by the inverted control model, and presenting the set of control parameters and associated values on a graphical user interface (gui) of an electronic display. other embodiments are described and claimed.
Inventor(s): Alvaro Garcia de Gorordo of Austin TX US for applied materials, inc., Michael T. Nichols of Eden Prairie MN US for applied materials, inc., Shreeram Dash of Newark CA US for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32522
Abstract: semiconductor processing systems and system components are described for mitigating lid heating of a plasma processing chamber. one system includes a plasma-based processing chamber enclosing a processing region, the processing chamber comprising a first portion including sidewalls and a bottom and a second portion including a chamber lid; a substate support within the processing chamber and configured to retain a first substrate in the processing region of the chamber; an inductively coupled plasma source configured to direct rf energy into the chamber; a conductive structure proximate to the chamber lid on an exterior side of the processing chamber; and a power source configured to apply a negative charge to the conductive structure that generates an electric field through the chamber lid, the electric filed providing repulsion force to incident electrons.
Inventor(s): Shanshan Yao of San Jose CA US for applied materials, inc., Xinyi Lu of Santa Clara CA US for applied materials, inc., Bo Xie of San Jose CA US for applied materials, inc., Chi-I Lang of Cupertino CA US for applied materials, inc., Li-Qun Xia of Cupertino CA US for applied materials, inc.
IPC Code(s): H01L21/02
CPC Code(s): H01L21/02211
Abstract: exemplary semiconductor processing methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. the deposition precursors may include a silicon-carbon-and-nitrogen-containing precursor. a substrate may be disposed within the processing region. the methods may include forming plasma effluents of the deposition precursors. the methods may include depositing a layer of silicon-carbon-and-nitrogen-containing material on the substrate. the layer of silicon-carbon-and-nitrogen-containing material may be characterized by a dielectric constant of less than or about 4.0. the layer of silicon-carbon-and-nitrogen-containing material may be characterized by a leakage current at 2 mv/cm of less than or about 3e-08 a/cm.
Inventor(s): John Bae of Pleasanton CA US for applied materials, inc., Praket Prakash Jha of San Jose CA US for applied materials, inc., Shuchi Sunil Ojha of Sunnyvale CA US for applied materials, inc., Jingmei Liang of San Jose CA US for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/3065
CPC Code(s): H01L21/02274
Abstract: exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. a substrate including one or more features may be housed within the processing region. the methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. the methods may include forming plasma effluents of the silicon-containing precursor and the hydrogen-containing precursor. the methods may include depositing a silicon-containing material on the substrate. the silicon-containing material may extend into the one or more features.
Inventor(s): Vikram M. BHOSLE of North Reading MA US for applied materials, inc., Hans-Joachim L. GOSSMANN of Summit NJ US for applied materials, inc., Stephen E. KRAUSE of Ipswich MA US for applied materials, inc., Deven Raj MITTAL of Middleton MA US for applied materials, inc., Hiroyuki ITO of Narita JP for applied materials, inc.
IPC Code(s): H01L21/02, C23C14/48, C30B25/18, C30B29/68, C30B31/06, C30B31/22, H01J37/32, H01L21/67
CPC Code(s): H01L21/02658
Abstract: disclosed herein are methods for passivating sic substrate defects using a low-energy treatment. in some embodiments, a method may include providing a silicon carbide (sic) substrate, treating the sic substrate using an ion implant or a plasma doping process, forming a first epitaxial layer over an upper surface of the sic substrate after the sic substrate is treated, and forming a second epitaxial layer over the first epitaxial layer.
Inventor(s): Yi Yang of San Jose CA US for applied materials, inc., Krishna Nittala of San Jose CA US for applied materials, inc., Rui Cheng of San Jose CA US for applied materials, inc., Karthik Janakiraman of San Jose CA US for applied materials, inc., Diwakar Kedlaya of San Jose CA US for applied materials, inc., Zubin Huang of Santa Clara CA US for applied materials, inc., Aykut Aydin of Sunnyvale CA US for applied materials, inc.
IPC Code(s): H01L21/033, C23C16/38
CPC Code(s): H01L21/0337
Abstract: exemplary semiconductor processing methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber. the methods may include flowing a boron-containing precursor into the substrate processing region of the semiconductor processing chamber. the methods may include depositing a boron-and-silicon-containing layer on a substrate in the substrate processing region of the semiconductor processing chamber. the boron-and-silicon-containing layer may be characterized by an increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer opposite the first surface. a flow rate of the boron-containing precursor may be increased during the deposition of the boron-and-silicon-containing layer.
Inventor(s): Jiayin Huang of Fremont CA US for applied materials, inc., Zihui Li of Santa Clara CA US for applied materials, inc., Yi Jin of San Mateo CA US for applied materials, inc., Anchuan Wang of San Jose CA US for applied materials, inc., Nitin K. Ingle of San Jose CA US for applied materials, inc.
IPC Code(s): H01L21/3065, H01L21/02
CPC Code(s): H01L21/3065
Abstract: exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. a substrate may be housed within the processing region. a first layer of silicon-and-germanium-containing material, a second layer of silicon-and-germanium-containing material, and a layer of silicon-containing material may be disposed on the substrate. the methods may include contacting the substrate with the oxygen-containing precursor. the contacting may oxidize at least a portion of the second layer of silicon-and-germanium-containing material. the methods may include providing a first etchant precursor to the processing region and contacting the substrate with the first etchant precursor. the contacting may selectively etch the first layer of silicon-and-germanium-containing material. the methods may include providing a second etchant precursor to the processing region. the methods may include contacting the substrate with the second etchant precursor. the contacting may etch a portion of the layer of silicon-containing material.
20250112052. DIRECTIONAL RIE FEATURE RECTANGULARITY_simplified_abstract_(applied materials, inc.)
Inventor(s): Yi-Hsin CHEN of Bedford MA US for applied materials, inc., Kevin R. Anglin of Somerville MA US for applied materials, inc., Yong Yang of Brookline MA US for applied materials, inc., Solomon Belangedi Basame of Middleton MA US for applied materials, inc., Yung-Chen Lin of Westwood MA US for applied materials, inc., Gang Shu of Hillsboro OR US for applied materials, inc.
IPC Code(s): H01L21/3065
CPC Code(s): H01L21/3065
Abstract: disclosed herein are methods for forming opening ends within semiconductor structures. in some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. the method may further include performing an ion etch to the opening by delivering an ion beam at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etch comprises a lean-gas chemistry, and wherein the ion etch causes the layer of the semiconductor device to be removed faster along the set of curved sections than along the set of sidewalls.
Inventor(s): Yuriy Shusterman of Ballston Lake NY US for applied materials, inc., Sean Reidy of Clifton Park NY US for applied materials, inc., Sai Hooi Yeong of Cupertino CA US for applied materials, inc., Lisa Megan McGill of Hillsboro OR US for applied materials, inc., Benjamin Colombeau of San Jose CA US for applied materials, inc., Andre P. Labonte of Mechanicville NY US for applied materials, inc., Veeraraghavan S. Basker of Fremont CA US for applied materials, inc., Balasubramanian Pranatharthiharan of San Jose CA US for applied materials, inc.
IPC Code(s): H01L21/3065, H01L21/02, H01L21/26, H01L21/311
CPC Code(s): H01L21/3065
Abstract: exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. a structure may be disposed within the processing region. the structure may include a first silicon-containing material. the structure may include a second silicon-containing material, an oxygen-containing material, or both. the methods may include contacting the structure with the etchant precursor. the contacting with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. the methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. the methods may include contacting the structure with the carbon-containing precursor. the contacting with the carbon-containing precursor may replenish carbon in the first silicon-containing material.
Inventor(s): Sonam Dorje Sherpa of San Ramon CA US for applied materials, inc., Alok Ranjan of San Ramon CA US for applied materials, inc.
IPC Code(s): H01L21/311
CPC Code(s): H01L21/31116
Abstract: exemplary semiconductor processing methods may include a substrate housed in the processing region. a layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. the methods may include providing a hydrogen-containing precursor, a nitrogen-containing precursor, or both to a processing region of a semiconductor processing chamber, forming plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor, and contacting the substrate with the plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor. the contacting may remove a portion of the layer of carbon-containing material. the methods may include providing a fluorine-containing precursor to the processing region, forming plasma effluents of the fluorine-containing precursor, and contacting the substrate with the plasma effluents of the fluorine-containing precursor.
Inventor(s): Alexander SULYMAN of Santa Clara CA US for applied materials, inc., Timothy Joseph FRANKLIN of Campbell CA US for applied materials, inc., Jaeyong CHO of San Jose CA US for applied materials, inc., Joseph F. SOMMERS of San Jose CA US for applied materials, inc., Joseph F. BEHNKE of Santa Clara CA US for applied materials, inc., Sajad YAZDANI of Santa Clara CA US for applied materials, inc., Xue CHANG of San Jose CA US for applied materials, inc., Kartik RAMASWAMY of San Jose CA US for applied materials, inc., Tomoaki KOHZU of Santa Clara CA US for applied materials, inc., Kyounghwan NA of Santa Clara CA US for applied materials, inc.
IPC Code(s): H01L21/683, H01J37/32, H01L21/67, H01L21/687
CPC Code(s): H01L21/6833
Abstract: embodiments of the present disclosure herein include an apparatus for processing a substrate. more specifically, embodiments of this disclosure provide a substrate support assembly that includes an electrostatic chuck (esc) assembly. the esc assembly comprises a cooling base having a top surface and an outer diameter sidewall, an esc having a substrate support surface, a bottom surface and an outer diameter sidewall, the bottom surface of the esc coupled to the top surface of the cooling base by a metal bond layer. the substrate support assembly includes a blocking ring disposed around the metal bond layer.
Inventor(s): Michael R. RICE of Pleasanton CA US for applied materials, inc., Vijay D. PARKHE of San Jose CA US for applied materials, inc.
IPC Code(s): H01L21/683, H01J37/32, H01L21/67
CPC Code(s): H01L21/6833
Abstract: disclosed herein is a substrate support assembly having a ground electrode mesh disposed therein along a side surface of the substrate support assembly. the substrate support assembly has a body. the body has an outer top surface, an outer side surface and an outer bottom surface enclosing an interior of the body. the body has a ground electrode mesh disposed in the interior of the body and adjacent the outer side surface, wherein the ground electrode does not extend through to the outer top surface or the outer side surface.
20250112082. WAFER LIFT PIN GUIDE_simplified_abstract_(applied materials, inc.)
Inventor(s): Hugo RIVERA of Santa Clara CA US for applied materials, inc.
IPC Code(s): H01L21/687
CPC Code(s): H01L21/68742
Abstract: embodiments of the present disclosure generally relate to a lift pin guide. the lift pin guide includes a cylindrical main section, a flange, a cylindrical recess, a cylindrical extension, and a bore. the flange is disposed at a first end of the cylindrical main section and has a diameter greater than a diameter of the cylindrical main section. the cylindrical recess is formed in a first surface of the flange, the first surface of the flange being opposite the cylindrical main section, and the cylindrical recess having an outer diameter less than the diameter of the cylindrical main section. the cylindrical extension protrudes beyond the first surface of the flange, the cylindrical extension being concentric with the cylindrical main section. the bore is formed through the cylindrical main section and the cylindrical extension.
Inventor(s): Ge Qu of Sunnyvale CA US for applied materials, inc., Zhiyuan Wu of San Jose CA US for applied materials, inc., Feng Chen of San Jose CA US for applied materials, inc., Carmen Leal Cervantes of Mountain View CA US for applied materials, inc., Yong Jin Kim of Albany CA US for applied materials, inc., Kevin Kashefi of San Ramon CA US for applied materials, inc., Xianmin Tang of San Jose CA US for applied materials, inc., Wenjing Xu of San Jose CA US for applied materials, inc., Lu Chen of Cupertino CA US for applied materials, inc., Tae Hong Ha of San Jose CA US for applied materials, inc.
IPC Code(s): H01L21/768, H01L21/285, H01L23/532
CPC Code(s): H01L21/76846
Abstract: methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. a self-assembled monolayer (sam) is formed on the bottom of the gap, and a barrier layer is formed on the sam before selectively depositing a metal liner on the barrier layer. the sam is removed after selectively depositing the metal liner on the barrier layer.
Inventor(s): Jianqiu GUO of San Jose CA US for applied materials, inc., Dong WANG of Zhuhai CN for applied materials, inc., Liqi WU of San Jose CA US for applied materials, inc., Yiyang WAN of Sunnyvale CA US for applied materials, inc., Shumao ZHANG of San Jose CA US for applied materials, inc., Qihao ZHU of Sunnyvale CA US for applied materials, inc., Weifeng YE of San Jose CA US for applied materials, inc., Jiang LU of Milpitas CA US for applied materials, inc., Shihchung CHEN of Cupertino CA US for applied materials, inc.
IPC Code(s): H01L21/768, C23C16/02, C23C16/42, C23C16/455, H01J37/32, H01L21/285, H01L23/532
CPC Code(s): H01L21/76889
Abstract: a contact structure includes a cavity comprising a device contact formed on a surface of a substrate, a bottom surface, and sidewalls. a metal silicide layer disposed over the surface of the device contact, the bottom surface, and the sidewalls of the cavity, and a treated surface formed over a portion of the metal silicide layer disposed over the sidewalls of the cavity.
20250113522. 3D Memory Mold Film Stack_simplified_abstract_(applied materials, inc.)
Inventor(s): Ruiying HAO of Santa Clara CA US for applied materials, inc., Fredrick David FISHBURN of Aptos CA US for applied materials, inc., Raghuveer Satya MAKALA of Campbell CA US for applied materials, inc., Thomas John KIRSCHENHEITER of Tempe AZ US for applied materials, inc., Balasubramanian PRANATHARTHIHARAN of San Jose CA US for applied materials, inc.
IPC Code(s): H01L29/775, H01L21/02, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H10D30/43
Abstract: three-dimensional (3d) memory structures and methods of formation of same are provided herein. in some embodiments, a 3d memory fabrication structure includes: a base silicon (si) layer; a silicon germanium (sige) layer disposed above the base si layer; and a doped silicon (si) layer disposed on at least one side of the sige layer, wherein the doped si layer contains a dopant that is at least one of carbon (c) or boron (b).
Inventor(s): Veeraraghavan S. Basker of Fremont CA US for applied materials, inc., Sai Hooi Yeong of Cupertino CA US for applied materials, inc., Ashish Pal of San Ramon CA US for applied materials, inc., El Mehdi Bazizi of San Jose CA US for applied materials, inc., Benjamin Colombeau of San Jose CA US for applied materials, inc., Balasubramanian Pranatharthiharan of San Jose CA US for applied materials, inc.
IPC Code(s): H01L29/66, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): H10D64/021
Abstract: embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (finfets) in particular, and methods of manufacturing such devices having improved effective capacitance (c). the finfets include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (c) of the device.
Inventor(s): Wenhui LI of Santa Clara CA US for applied materials, inc., Kevin CHEN of Santa Clara CA US for applied materials, inc., Wen-Hao WU of San Jose CA US for applied materials, inc., Yu-Min WANG of Santa Clara CA US for applied materials, inc., Zongkai WU of Santa Clara CA US for applied materials, inc., Kwang Soo HUH of Palo Alto CA US for applied materials, inc., Lai ZHAO of Campbell CA US for applied materials, inc.
IPC Code(s): H10K59/80, C23C16/34, C23C16/455, C23C16/50
CPC Code(s): H10K59/873
Abstract: embodiments described herein relate to an optical device and methods of forming an optical device. the optical device includes a substrate, an illumination source, a capping layer, an encapsulation layer, and a passivation layer. the encapsulation layer includes a first atomic layer deposition (ald) layer, a chemical vapor deposition (cvd) layer, and a second ald layer. the method includes disposing a capping layer over an illumination layer, the illumination layer disposed over a substrate in a processing chamber; disposing a first atomic layer deposition (ald) layer over the capping layer; disposing a chemical vapor deposition (cvd) layer over the first ald layer; disposing a second ald layer over the cvd layer; and disposing a passivation layer over the second ald layer.
Applied Materials, Inc. patent applications on April 3rd, 2025
- Applied Materials, Inc.
- B24B37/005
- B24B37/04
- B24B37/24
- B24B49/16
- CPC B24B37/005
- Applied materials, inc.
- B24B49/12
- B24B37/015
- B24B37/10
- B24B49/02
- B24B49/04
- B24B49/14
- B24B55/02
- B24B57/02
- CPC B24B37/015
- B24B37/26
- CPC B24B37/107
- B24B37/32
- CPC B24B37/32
- C23C14/54
- C23C14/14
- C23C14/24
- G01B17/02
- CPC C23C14/54
- G01B5/14
- B05C21/00
- B25J9/16
- CPC G01B5/14
- H01J37/317
- H01J37/304
- CPC H01J37/3171
- H01J37/32
- CPC H01J37/32522
- H01L21/02
- CPC H01L21/02211
- H01L21/3065
- CPC H01L21/02274
- C23C14/48
- C30B25/18
- C30B29/68
- C30B31/06
- C30B31/22
- H01L21/67
- CPC H01L21/02658
- H01L21/033
- C23C16/38
- CPC H01L21/0337
- CPC H01L21/3065
- H01L21/26
- H01L21/311
- CPC H01L21/31116
- H01L21/683
- H01L21/687
- CPC H01L21/6833
- CPC H01L21/68742
- H01L21/768
- H01L21/285
- H01L23/532
- CPC H01L21/76846
- C23C16/02
- C23C16/42
- C23C16/455
- CPC H01L21/76889
- H01L29/775
- H01L29/423
- H01L29/66
- H01L29/786
- CPC H10D30/43
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/78
- CPC H10D64/021
- H10K59/80
- C23C16/34
- C23C16/50
- CPC H10K59/873