Apple inc. (20240103238). 3D System and Wafer Reconstitution with Mid-layer Interposer simplified abstract
3D System and Wafer Reconstitution with Mid-layer Interposer
Organization Name
Inventor(s)
Sanjay Dabral of Cupertino CA (US)
SivaChandra Jangam of Milpitas CA (US)
3D System and Wafer Reconstitution with Mid-layer Interposer - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240103238 titled '3D System and Wafer Reconstitution with Mid-layer Interposer
Simplified Explanation
The patent application describes a system in package structure and method of fabrication using wafer reconstitution. In one embodiment, a 3D system includes a mid-layer interposer, a first package level underneath the mid-layer interposer, and a second package level over the mid-layer interposer. Components in the second package level can be bonded to the mid-layer interposer with metal-metal bonds and optionally dielectric-dielectric bonds, while components in the first package level can be bonded to the mid-layer interposer with dielectric-dielectric and optionally metal-metal bonds. Dies within the first and/or second package levels may be connected with one or more optical interconnect paths.
- System in package structure with mid-layer interposer
- Fabrication method using wafer reconstitution
- Metal-metal and dielectric-dielectric bonds for component bonding
- Optional optical interconnect paths for dies
- 3D system design with first and second package levels
Potential Applications
The technology described in the patent application could be applied in the development of advanced electronic devices, such as high-performance computing systems, mobile devices, and IoT devices.
Problems Solved
This technology addresses the challenge of integrating multiple components in a compact and efficient manner, enabling higher performance and functionality in electronic devices.
Benefits
The benefits of this technology include improved system integration, increased performance, reduced footprint, and enhanced reliability of electronic devices.
Potential Commercial Applications
The potential commercial applications of this technology include semiconductor manufacturing, consumer electronics, telecommunications, and automotive industries.
Possible Prior Art
One possible prior art for this technology could be the use of 3D packaging techniques in semiconductor industry, such as through-silicon vias (TSVs) and stacked die technologies.
Unanswered Questions
How does this technology compare to traditional 2D packaging methods?
The article does not provide a direct comparison between this technology and traditional 2D packaging methods in terms of performance, cost, and scalability.
What are the limitations of this technology in terms of scalability and manufacturability?
The article does not address the potential limitations of this technology in scaling up for mass production and the challenges in manufacturing complex 3D systems.
Original Abstract Submitted
a system in package structure and method of fabrication using wafer reconstitution are described. in an embodiment a 3d system includes a mid-layer interposer a first package level underneath the mid-layer interposer and a second package level over the mid-layer interposer. second package level components can be bonded to the mid-layer interposer with metal-metal bonds and optionally dielectric-dielectric bonds, while the first package level components can be bonded to the mid-layer interposer with dielectric-dielectric and optionally metal-metal bonds. dies within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.
