Advanced Micro Devices, Inc. patent applications on January 2nd, 2025
Patent Applications by Advanced Micro Devices, Inc. on January 2nd, 2025
Advanced Micro Devices, Inc.: 36 patent applications
Advanced Micro Devices, Inc. has applied for patents in the areas of G06T15/04 (4), G06F3/06 (4), G06F9/48 (3), G06T15/00 (2), G06F12/0802 (2) G06F9/4881 (2), G06T15/04 (2), G06F3/0625 (2), A63F13/77 (1), G06T15/005 (1)
With keywords such as: memory, circuit, data, based, processing, circuitry, device, signal, also, and space in patent application abstracts.
Patent Applications by Advanced Micro Devices, Inc.
20250001312. CROWDSOURCED CLOUD GAMING_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Le Zhang of Markham (CA) for advanced micro devices, inc., Wei Liang of Markham (CA) for advanced micro devices, inc., Ilia Blank of Markham (CA) for advanced micro devices, inc., Patrick Pak Kin Fok of Markham (CA) for advanced micro devices, inc., Eleftherios Makedon of Markham (CA) for advanced micro devices, inc., Amir Alam of Markham (CA) for advanced micro devices, inc., Sebastian Borkowski of Oshawa (CA) for advanced micro devices, inc., Goverdhan Aligeti of Hyderabad (IN) for advanced micro devices, inc.
IPC Code(s): A63F13/77, A63F13/335, A63F13/35
CPC Code(s): A63F13/77
Abstract: systems and methods for crowdsourcing cloud application execution are described. an application system receives, from a client device, a first request to initiate an application session. the application system identifies a host device to fulfill the first request. the application system then initiates execution of the application session on the host device and generates, for the client device, a plurality of controls to control the application session executing on the host device. the host device is incentivized for each application session hosted.
Inventor(s): Josip Popovic of Markham (CA) for advanced micro devices, inc., Anshuman Mittal of Santa Clara CA (US) for advanced micro devices, inc., Kellie Marks of Sydney (AU) for advanced micro devices, inc.
IPC Code(s): G06F1/26
CPC Code(s): G06F1/26
Abstract: an apparatus and method for efficiently managing voltage droop among replicated compute circuits of an integrated circuit. in various implementations, an integrated circuit includes multiple, replicated compute circuits, each with the circuitry of multiple lanes of execution. control circuitry of the integrated circuit identifies, early in execution pipelines, groups of instructions to be executed by a corresponding compute circuit, and generates a total power consumption estimate for the groups. the control circuitry maintains n previous total power consumption estimates, and stores the n power consumption estimates in staging circuitry referred to as an “instruction history pipeline.” if any differences between total power consumption estimates of different stages of the instruction history pipeline exceeds a corresponding threshold, then the control circuitry reduces, late in the execution pipeline, the rate of instruction execution of computation lanes of a corresponding compute circuit.
Inventor(s): Gregg Donley of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06F9/30
CPC Code(s): G06F1/3253
Abstract: the disclosed device includes multiple data elements each configured to send a bit of a bit sequence by toggling at most half of a number of bits from a previously sent bit sequence. the bit sequence can first be biased and then xored with the previously sent bit sequence. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Benjamin Tsien of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06F1/3296, G06F1/3234
CPC Code(s): G06F1/3296
Abstract: the disclosed device includes heterogeneous chiplets that can communicate when each of the heterogenous chiplets has locally reached an idle state. once receiving confirmations of the idle state from each of the heterogenous chiplets, the chiplets can complete the entry of the low power state. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Kevin M. Brandl of Austin TX (US) for advanced micro devices, inc., Jean J. Chittilappilly of Maynard MA (US) for advanced micro devices, inc., Tahsin Askar of Round Rock TX (US) for advanced micro devices, inc., James R. Magro of Lakeway TX (US) for advanced micro devices, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: a memory accessing circuit includes a memory controller for scheduling accesses to a memory, and a physical interface circuit for driving signals to the memory according to scheduled accesses and having configuration data. the memory controller comprises a memory and is responsive to a low power mode entry signal to save the configuration data in the memory. the physical interface circuit removes operating power from circuitry in the physical interface circuit that stores the configuration data in response to the memory controller completing a save operation.
Inventor(s): Benjamin Tsien of Santa Clara CA (US) for advanced micro devices, inc., Chintan S. Patel of Austin TX (US) for advanced micro devices, inc., Guhan Krishnan of Boxborough MA (US) for advanced micro devices, inc.
IPC Code(s): G06F3/06, G06F12/0802
CPC Code(s): G06F3/0625
Abstract: the disclosed device includes multiple processing component, and a cache. one of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. the memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. various other methods, systems, and computer-readable media are also disclosed.
20250004653. DYNAMIC MEMORY RECONFIGURATION_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Mark Fowler of Boxborough MA (US) for advanced micro devices, inc., Anthony Asaro of Markham (CA) for advanced micro devices, inc., Vydhyanathan Kalyanasundharam of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0631
Abstract: a processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. in some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.
Inventor(s): Emily Anne Furst of Duvall WA (US) for advanced micro devices, inc., Robin Conradine Knauerhase of Portland OR (US) for advanced micro devices, inc., Sangeeta Chowdhary of Sunnyvale CA (US) for advanced micro devices, inc., Michael L. Chu of San Jose CA (US) for advanced micro devices, inc.
IPC Code(s): G06F8/41
CPC Code(s): G06F8/41
Abstract: selecting intermediate representation transformation for compilations is described. in accordance with the described techniques, source code is received to be compiled by a compilation system for execution by a processor of hardware. intermediate representation transformations are selected for the source code based on system load information associated with the hardware. the intermediate representation transformations are output to the compilation system.
Inventor(s): Hashim Sharif of Chatham IL (US) for advanced micro devices, inc., Johnathan Robert Alsop of Seattle WA (US) for advanced micro devices, inc.
IPC Code(s): G06F8/41
CPC Code(s): G06F8/443
Abstract: cross-component optimizing compiler systems are described. in accordance with the described techniques, machine learning models receive components of source code to be compiled. the machine learning models generate component prediction functions for the components of the source code. a tuning engine selects parameters for the components of the source code based on the component prediction functions. domain-specific language compilers compile the source code based on the selected parameters.
Inventor(s): Wei Huang of Shanghai (CN) for advanced micro devices, inc., ZhongXiang Luo of Shanghai (CN) for advanced micro devices, inc., ShengNan Xu of Shanghai (CN) for advanced micro devices, inc., LingPeng Jin of Shanghai (CN) for advanced micro devices, inc.
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4812
Abstract: a processing unit monitors, over a sliding time window, the number of instructions dispatched for execution at the processing unit. in response to the number of instructions exceeding a threshold, the processing unit throttles (e.g., pauses) the dispatch of instructions for a specified amount of time. the processing unit thus ensures that the number of dispatched instructions does not change too rapidly in too short a period of time reducing the likelihood of sudden changes in processing unit current, without unduly impacting the performance of the processing unit across all workloads.
Inventor(s): Mark Unruh Wyse of Bellevue WA (US) for advanced micro devices, inc., Anthony Thomas Gutierrez of Seattle WA (US) for advanced micro devices, inc., Stephen Alexander Zekany of Redmond WA (US) for advanced micro devices, inc., Paul Blinzer of Carnation WA (US) for advanced micro devices, inc.
IPC Code(s): G06F9/455
CPC Code(s): G06F9/45558
Abstract: a processing unit (e.g., a cpu) executes multiple processes, such as multiple virtual machines, wherein each process employs virtual signals and virtual signal monitors to support signaling between the process and one or more accelerators. a hardware signal manager (hsm) assigns each virtual signal to a physical signal of the system and assigns each virtual signal monitor to a physical signal monitor. based on a process' interactions (e.g., signal operations) with a virtual signal monitor, the hsm executes corresponding interactions at the assigned physical signal monitor. the hsm thus virtualizes the physical signal monitors for the executing processes.
Inventor(s): Alexandru Dutu of Kirkland WA (US) for advanced micro devices, inc., Niti Madan of Bee Cave TX (US) for advanced micro devices, inc.
IPC Code(s): G06F9/48, G06F12/08
CPC Code(s): G06F9/4881
Abstract: scheduling requests of multiple processing-in-memory threads and requests of multiple non-processing-in-memory threads is described. in accordance with the described techniques, a memory controller receives a plurality of processing-in-memory threads and a plurality of non-processing-in-memory threads from a host. the memory controller schedules an order of execution for requests of the plurality of processing-in-memory threads and requests of the plurality of non-processing-in-memory threads based on a priority associated with each of the requests and a current operating mode of the system. requests are maintained in queues at the memory controller and are individually assigned a priority level based on time enqueued at the memory controller. requests of a different mode than a current operating mode of the system are delayed for scheduling until at least one different mode request is escalated to a maximum priority value, at which point the memory controller initiates a system mode switch.
20250004828. HARDWARE-BASED ACCELERATOR SIGNALING_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Mark Unruh Wyse of Bellevue WA (US) for advanced micro devices, inc., Anthony Thomas Gutierrez of Seattle WA (US) for advanced micro devices, inc., Paul Blinzer of Carnation WA (US) for advanced micro devices, inc., Samuel Richard Bayliss of San Jose CA (US) for advanced micro devices, inc.
IPC Code(s): G06F9/48, G06F9/38
CPC Code(s): G06F9/4881
Abstract: a processor employs a hardware signal monitor to manage signaling for accelerators. the hardware signal monitor monitors designated memory addresses assigned to accelerator signals. in response to a memory write to one of the designated memory addresses, the hardware signal monitor executes a set of one or more operations (referred to as a callback). the hardware signal monitor thereby enables improved and enhanced signaling features, such as asynchronous signaling between agents, inter-accelerator signaling, and inter-process signaling.
Inventor(s): Sudhanva Gurumurthi of Austin TX (US) for advanced micro devices, inc., Vilas Sridharan of Boston MA (US) for advanced micro devices, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1004
Abstract: a processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. in response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. the memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. after receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. in response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.
Inventor(s): Keith Lowery of Garland TX (US) for advanced micro devices, inc.
IPC Code(s): G06F11/34, G06F11/30
CPC Code(s): G06F11/3466
Abstract: techniques are described for adaptive application profiling, such as for adaptively collecting profiling runtime data for an application running on heterogeneous processing architectures. a first set of profiling data is collected from a first set of tracking circuitry during execution of an application by one or more processors. during the execution of the application and based on the first set of profiling data, a second set of tracking circuitry is determined for use in collecting additional profiling data for the application, the second set of tracking circuitry being distinct from the first set of tracking circuitry. a second set of runtime profiling data is collected from the second set of tracking circuitry.
20250004943. RUNNING AVERAGE CACHE HIT RATE_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Edgar Munoz of Austin TX (US) for advanced micro devices, inc., Chintan S. Patel of Austin TX (US) for advanced micro devices, inc., Gregg Donley of Santa Clara CA (US) for advanced micro devices, inc., Vydhyanathan Kalyanasundharam of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0802
Abstract: the disclosed device includes a first register that stores a cumulative delta value and a second register that stores an average cache hit rate. the device also includes a control circuit that calculates a cache hit rate and updates the cumulative delta value based on the cache hit rate and the average cache hit rate. the control circuit also updates the average cache hit rate based on the updated cumulative delta value, and can update a cache allocation policy based on the updated average cache hit rate. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Anthony Thomas Gutierrez of Seattle WA (US) for advanced micro devices, inc., Todd David Basso of Arlington MA (US) for advanced micro devices, inc., Gabriel Hsiuwei Loh of Bellevue WA (US) for advanced micro devices, inc.
IPC Code(s): G06F13/16, G06F13/366
CPC Code(s): G06F13/1668
Abstract: programmable i/o die devices and methods are described. an example system includes an input/output die (iod) that couples a plurality of devices. the system also includes a programmable fabric included in the iod. the programmable fabric implements interconnects for connecting the plurality of devices according to a reconfigurable topology defined by a configuration of the programmable fabric.
Inventor(s): William Peter Ehrett of Austin TX (US) for advanced micro devices, inc., Anthony Gutierrez of Bellevue WA (US) for advanced micro devices, inc., Vedula Venkata Srikant Bharadwaj of Bellevue WA (US) for advanced micro devices, inc., Karthik Ramu Sangaiah of Bellevue WA (US) for advanced micro devices, inc., Prachi Shukla of Santa Clara CA (US) for advanced micro devices, inc., Sriseshan Srikanth of Austin TX (US) for advanced micro devices, inc., Ganesh Dasika of Austin TX (US) for advanced micro devices, inc., John Kalamatianos of Boxborough MA (US) for advanced micro devices, inc.
IPC Code(s): G06F13/36
CPC Code(s): G06F13/36
Abstract: a semiconductor device, referred to herein as a globally interconnected operations (gio) layer, provides global operations in the form of global data reduction for one or more pe arrays. the gio layer includes processing elements that perform global data reduction on processing results from one or more pe arrays. the gio layer includes connectors that allow it to be arranged in a 3d stack with one or more pe arrays, for example, on top of or beneath a pe array. this allows reduction operations to be implemented across pe arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of pe arrays, and without being constrained by particular pe array designs.
Inventor(s): BUHENG XU of BEIJING (CN) for advanced micro devices, inc., XIAO HAN of SUZHOU (CN) for advanced micro devices, inc., PHILIP NG of MARKHAM (CA) for advanced micro devices, inc., SHIWU YANG of SUZHOU (CN) for advanced micro devices, inc.
IPC Code(s): G06F13/42
CPC Code(s): G06F13/42
Abstract: an apparatus translates transaction requests using a bus protocol translation lookup table (lut) that comprises bus protocol translation data. a bus protocol translation controller generates the outgoing translated transaction request by translating the incoming transaction request using the bus protocol translation data from the bus protocol translation lut. the controller translates a received response from the target unit to a response in a first bus protocol for a corresponding requesting unit. associated methods are also presented. in some examples, the bus protocol translation data corresponds to each of a plurality of requesting units for translating between an incoming transaction request sent via a first bus protocol to an outgoing translated transaction request sent via a second bus protocol for the at least one target unit.
20250004982. NON-HOMOGENEOUS CHIPLETS_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Matthaeus G. Chajdas of Munich (DE) for advanced micro devices, inc.
IPC Code(s): G06F15/80, G06F15/76, G06T15/00
CPC Code(s): G06F15/80
Abstract: a semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. an interconnect communicatively couples the semiconductor dies together. commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.
Inventor(s): Laurent S. White of Austin TX (US) for advanced micro devices, inc., Darian Osahar Nwankwo of Ithaca NY (US) for advanced micro devices, inc., Gurpreet Singh Hora of New York NY (US) for advanced micro devices, inc.
IPC Code(s): G06F30/27
CPC Code(s): G06F30/27
Abstract: method and devices are provided for performing a physics-based simulation. a processing devices comprises memory and a processor. the processor is configured to perform a physics-based simulation by executing a portion of the physics-based simulation, training a neural network model based on results from executing the first portion of the physics-based simulation, performing inference processing based on the results of the training of the neural network model and providing a prediction, based on the inference processing, as an input back to the physics-based simulation.
Inventor(s): Brian D. Emberling of Santa Clara CA (US) for advanced micro devices, inc., Joseph Lee Greathouse of Austin TX (US) for advanced micro devices, inc., Anthony Thomas Gutierrez of Bellevue WA (US) for advanced micro devices, inc.
IPC Code(s): G06T1/60, G06F9/38, G06T1/20
CPC Code(s): G06T1/60
Abstract: systems, apparatuses, and methods for implementing register compaction with early release are disclosed. a processor includes at least a command processor, a plurality of compute units, a plurality of registers, and a control unit. registers are statically allocated to wavefronts by the control unit when wavefronts are launched by the command processor on the compute units. in response to determining that a first set of registers, previously allocated to a first wavefront, are no longer needed, the first wavefront executes an instruction to release the first set of registers. the control unit detects the executed instruction and releases the first set of registers to the available pool of registers to potentially be used by other wavefronts. then, the control unit can allocate the first set of registers to a second wavefront for use by threads of the second wavefront while the first wavefront is still active.
Inventor(s): Michal Adam Wozniak of Santa Clara CA (US) for advanced micro devices, inc., Guennadi Riguer of Markham (CA) for advanced micro devices, inc.
IPC Code(s): G06T15/00, G06T15/04
CPC Code(s): G06T15/005
Abstract: a technique for rendering is provided. the technique includes generating a first gradient for a shade space texture tile, wherein the first gradient reflects a relationship between shade space texel spacing and screen space pixel spacing; generating a second gradient for a shade space texel of the shade space texture tile, wherein the second gradient reflects a relationship between material texel spacing and shade space texel spacing; combining the first gradient and the second gradient to obtain a third gradient; and performing anisotropic filtering on the material texture using the third gradient to obtain a value for the shade space texel.
Inventor(s): Guennadi Riguer of Markham (CA) for advanced micro devices, inc., Michal Adam Wozniak of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06T15/04, G06T3/40
CPC Code(s): G06T15/04
Abstract: a technique for texture filtering. a transition is made from a first mipmap corresponding to a first texture resolution to a second mipmap corresponding to a second texture resolution. the first texture resolution is lower than the second texture resolution. as compared to standard trilinear filtering, initiation of the transition is delayed by an offset (or bias), which serves to delay the initial use of the second mipmap until it has been loaded. following initiation of the transition, first and second weightings are selected with a nonlinear filter, and the system interpolates between the first mipmap and the second mipmap by applying the weightings. during an initial portion of the transition, the nonlinear filter has a slope that is higher than that of the standard trilinear filter.
Inventor(s): Michal Adam Wozniak of Santa Clara CA (US) for advanced micro devices, inc., Guennadi Riguer of Markham (CA) for advanced micro devices, inc.
IPC Code(s): G06T15/04, G06T7/73
CPC Code(s): G06T15/04
Abstract: a technique for sampling a primitive id map. the technique includes identifying a sample point having a location in a texture space; obtaining a primitive id sample from the primitive id map based on the location of the sample point in the texture space; identifying a primitive based on the primitive id; testing the location in the texture space for inclusion within the identified primitive; and selecting either the primitive id or a different primitive id based on the testing.
20250005842. NEURAL NETWORK-BASED RAY TRACING_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Shin Fujieda of Tokyo (JP) for advanced micro devices, inc., Takahiro Harada of Santa Clara CA (US) for advanced micro devices, inc., Chih-Chen Kao of Munich (DE) for advanced micro devices, inc.
IPC Code(s): G06T15/06
CPC Code(s): G06T15/06
Abstract: a technique for performing ray tracing operations is provided. the technique includes traversing a bounding volume hierarchy for a ray to arrive at a bounding box without use of a neural network; perform a feature vector lookup using modified polar coordinates characterizing the ray relative to the bounding box to obtain a set of feature vectors; and obtaining output with the neural network using the set of feature vectors.
Inventor(s): Guennadi Riguer of Markham (CA) for advanced micro devices, inc., Michal Adam Wozniak of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06T15/80, G06T15/04
CPC Code(s): G06T15/80
Abstract: a technique for rendering is provided. the technique includes determining a first correspondence between a screen space and a shade space in a visibility pass; selecting a size for a shade space tile based on the correspondence between the screen space and the shade space; and shading the shade space tile based on the material texture correspondence.
Inventor(s): Jonathan Philip Bonsor-Matthews of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06V20/40, G06V10/25, G06V10/26
CPC Code(s): G06V20/46
Abstract: a portable electronic device includes a video encoder. the video encoder is configured to receive a video frame. responsive to the video frame including at least one of a salient object or a region of interest, the video encoder is further configured to partition the video frame into one or more tiles based on a location of the at least one of the salient object or the region of interest.
Inventor(s): Ioannis Papadopoulos of Boxorough MA (US) for advanced micro devices, inc., Vignesh Adhinarayanan of Austin TX (US) for advanced micro devices, inc., Ashwin Aji of Santa Clara CA (US) for advanced micro devices, inc., Jagadish B. Kotra of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G11C7/10, G06F3/06
CPC Code(s): G11C7/1006
Abstract: an apparatus and method for creating less computationally intensive nodes for a neural network. an integrated circuit includes a host processor and multiple memory channels, each with multiple memory array banks. each of the memory array banks includes components of a processing-in-memory (pim) accelerator and a scatter and gather circuit used to dynamically perform quantization operations and dequantization operations that offload these operations from the host processor. the host processor executes a data model that represents a neural network. the memory array banks store a single copy of a particular data value in a single precision. therefore, the memory array banks avoid storing replications of the same data value with different precisions to be used by a neural network node. the memory array banks dynamically perform quantization operations and dequantization operations on one or more of the weight values, input data values, and activation output values of the neural network.
20250006246. RC-TUNED WORDLINE UNDERDRIVE CIRCUIT_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Russell Schreiber of Austin TX (US) for advanced micro devices, inc., Clinton Harold Parker of Fort Collins MA (US) for advanced micro devices, inc.
IPC Code(s): G11C11/408, G11C11/4076, H03K19/017
CPC Code(s): G11C11/4085
Abstract: an apparatus and method for both reducing power consumption and increasing read access stability of a memory array. an integrated circuit includes a memory array with memory bit cells arranged as multiple rows and multiple columns. the array also includes multiple word line driver circuits configured to generate a corresponding word line for multiple rows. the array includes an underdrive circuit configured to adjust, via a configurable resistor-capacitor circuit, a rate of change of a voltage level of a word line. the configurable resistor-capacitor circuit controls the store data rate of the charging of the selected word line and allows the selected word line to charge to the power supply voltage. the configurable resistor-capacitor circuit controls the rate of charging without creating a direct current path between the power supply voltage and the ground reference level that would increase power consumption.
Inventor(s): Nehal Patel of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G11C29/36, G11C29/12, G11C29/56
CPC Code(s): G11C29/36
Abstract: some implementations provide systems methods and devices for integrated circuit self-test. the integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. the integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. some implementations provide an integrated circuit configured for storing and reading data. the integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via bist circuitry of the first memory until a first bist counter saturates. the integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via bist circuitry of the second memory until a second bist counter saturates.
Inventor(s): CHIA CHUN MIAO of SANTA CLARA CA (US) for advanced micro devices, inc., SUNGJUN IM of SANTA CLARA CA (US) for advanced micro devices, inc., HIMANSHU A BAL of SANTA CLARA CA (US) for advanced micro devices, inc.
IPC Code(s): H01L21/033, H01L21/304, H01L23/367
CPC Code(s): H01L21/0337
Abstract: a method for forming a lid of a semiconductor assembly includes applying a mask to a surface of the lid to leave an area of the lid including a pedestal and wider than the pedestal included in the lid exposed. the method applies a thermally conductive material to the area of the surface of the lid that is exposed and removes at least a portion of the thermally conductive material from the surface of the lid.
Inventor(s): Ravi Kumar KALLEMPUDI of Bengaluru (IN) for advanced micro devices, inc., Robert Scott RUTH of Fort Collins CO (US) for advanced micro devices, inc., Suhas SHIVARAM of Bengaluru (IN) for advanced micro devices, inc.
IPC Code(s): H01L27/02, H01L21/8228, H02H9/04
CPC Code(s): H01L27/0255
Abstract: a semiconductor electrostatic discharge (esd) protection circuit comprises an n diode for limiting negative going voltages with reference to ground (v) and a p diode for limiting positive going voltages with reference to a positive supply voltage (v). the n-diode is formed in a single p-well surrounded by an n-well ring. the p-diode is formed in a single n-well surrounded by a p-well ring. the n-diode comprises a plurality of n+ fingers, each n+ finger is surrounded by a p+ guard ring. the p-diode comprises a plurality of p+ fingers, each p+ finger surrounded by an n+ guard ring. the plurality of n+ fingers and p+ fingers are coupled to an input-output pad. the p+ guard rings are coupled to ground (v) and the n+ guard rings are coupled to the positive supply voltage (v).
Inventor(s): Rajesh Kumar of Santa Clara CA (US) for advanced micro devices, inc., Edoardo Prete of Boxborough MA (US) for advanced micro devices, inc., Gerald R. Talbot of Boxborough MA (US) for advanced micro devices, inc., Ethan Crain of Boxborough MA (US) for advanced micro devices, inc., Tracy J. Feist of Fort Collins CO (US) for advanced micro devices, inc., Jeffrey Cooper of Fort Collins CO (US) for advanced micro devices, inc.
IPC Code(s): H03K19/0175, H03F3/45
CPC Code(s): H03K19/017509
Abstract: systems, apparatuses, and methods for implementing a combo scheme for direct current (dc) level shifting of signals are disclosed. a receiver circuit receives an input signal on a first interface. the first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. an op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a dc level shift of the input signal, and achieve linear equalization of the input signal.
Inventor(s): Bryan P. Broussard of Austin TX (US) for advanced micro devices, inc., Chintan S. Patel of Austin TX (US) for advanced micro devices, inc., Eric Christopher Morton of Austin TX (US) for advanced micro devices, inc., Jeffrey Lynn Freeman of Austin TX (US) for advanced micro devices, inc., Vydhyanathan Kalyanasundharam of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): H04L49/25
CPC Code(s): H04L49/25
Abstract: the disclosed device includes memory channel interfaces and mesh lanes each corresponding to a particular memory channel interface. the device also includes ports and various routing elements interconnecting the ports, mesh lanes, memory channel interfaces. the device further includes a control circuit configured to receive a data packet on a port, select a mesh lane based on a destination of the data packet, and forward the data packet to the selected mesh lane via a routing element. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Girish Anant Kini of Santa Clara CA (US) for advanced micro devices, inc., Ahmed Mohamed Abou-Alfotouh of Santa Clara CA (US) for advanced micro devices, inc., Shardul Suresh Adkar of Austin TX (US) for advanced micro devices, inc., Ethan Cruz of Austin TX (US) for advanced micro devices, inc., Salvador D. Jimenez, III of Austin TX (US) for advanced micro devices, inc., Mark Steinke of Austin TX (US) for advanced micro devices, inc., Edgar Stone of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20772
Abstract: a method for server level cooling can include providing a printed circuit board and attaching a cooling system to the printed circuit board. the cooling system can be configured for placement thereon of two or more expansion cards having back side power delivery components. various other methods, systems, and computer-readable media are also disclosed.
Advanced Micro Devices, Inc. patent applications on January 2nd, 2025
- Advanced Micro Devices, Inc.
- A63F13/77
- A63F13/335
- A63F13/35
- CPC A63F13/77
- Advanced micro devices, inc.
- G06F1/26
- CPC G06F1/26
- G06F9/30
- CPC G06F1/3253
- G06F1/3296
- G06F1/3234
- CPC G06F1/3296
- G06F3/06
- CPC G06F3/0625
- G06F12/0802
- CPC G06F3/0631
- G06F8/41
- CPC G06F8/41
- CPC G06F8/443
- G06F9/48
- CPC G06F9/4812
- G06F9/455
- CPC G06F9/45558
- G06F12/08
- CPC G06F9/4881
- G06F9/38
- G06F11/10
- G06F11/07
- CPC G06F11/1004
- G06F11/34
- G06F11/30
- CPC G06F11/3466
- CPC G06F12/0802
- G06F13/16
- G06F13/366
- CPC G06F13/1668
- G06F13/36
- CPC G06F13/36
- G06F13/42
- CPC G06F13/42
- G06F15/80
- G06F15/76
- G06T15/00
- CPC G06F15/80
- G06F30/27
- CPC G06F30/27
- G06T1/60
- G06T1/20
- CPC G06T1/60
- G06T15/04
- CPC G06T15/005
- G06T3/40
- CPC G06T15/04
- G06T7/73
- G06T15/06
- CPC G06T15/06
- G06T15/80
- CPC G06T15/80
- G06V20/40
- G06V10/25
- G06V10/26
- CPC G06V20/46
- G11C7/10
- CPC G11C7/1006
- G11C11/408
- G11C11/4076
- H03K19/017
- CPC G11C11/4085
- G11C29/36
- G11C29/12
- G11C29/56
- CPC G11C29/36
- H01L21/033
- H01L21/304
- H01L23/367
- CPC H01L21/0337
- H01L27/02
- H01L21/8228
- H02H9/04
- CPC H01L27/0255
- H03K19/0175
- H03F3/45
- CPC H03K19/017509
- H04L49/25
- CPC H04L49/25
- H05K7/20
- CPC H05K7/20772
