Advanced Micro Devices, Inc. patent applications on April 24th, 2025
Patent Applications by Advanced Micro Devices, Inc. on April 24th, 2025
Advanced Micro Devices, Inc.: 14 patent applications
Advanced Micro Devices, Inc. has applied for patents in the areas of G06T15/06 (3), G06F7/483 (2), G06F3/06 (1), H01L25/065 (1), H01L25/00 (1) G06T15/06 (3), G06F3/0611 (1), G06F7/483 (1), G06F7/49984 (1), G06F7/556 (1)
With keywords such as: data, memory, number, format, circuit, based, guest, multiple, hardware, and disclosed in patent application abstracts.
Patent Applications by Advanced Micro Devices, Inc.
Inventor(s): Vignesh Adhinarayanan of Austin TX US for advanced micro devices, inc., Shaizeen Dilawarhusen Aga of Santa Clara CA US for advanced micro devices, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: a system includes memory hardware including a memory and a processing-in-memory component. a system includes a host including at least one core. a system includes a memory controller including a scheduling system. the scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. the scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.
20250130767. FLOATING-POINT CONVERSION CIRCUIT_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Shubh Shah of Folsom CA US for advanced micro devices, inc., Ashutosh Garg of Folsom CA US for advanced micro devices, inc., Bin He of Orlando FL US for advanced micro devices, inc., Michael Mantor of Orlando FL US for advanced micro devices, inc., Shubra Marwaha of Santa Clara CA US for advanced micro devices, inc., Subramaniam Maiyuran of Folsom CA US for advanced micro devices, inc.
IPC Code(s): G06F7/483
CPC Code(s): G06F7/483
Abstract: the disclosed circuit can select micro-operations specifically for converting a value in a first number format to a second number format. the circuit can include micro-operations for various conversions between different number formats, including number formats of different floating-point precisions. various other methods, systems, and computer-readable media are also disclosed.
20250130769. STOCHASTIC ROUNDING CIRCUIT_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Shubh Shah of Santa Clara CA US for advanced micro devices, inc., Ashutosh Garg of Folsom CA US for advanced micro devices, inc., Bin He of Orlando FL US for advanced micro devices, inc., Michael Mantor of Orlando FL US for advanced micro devices, inc., Shubra Marwaha of Santa Clara CA US for advanced micro devices, inc., Subramaniam Maiyuran of Folsom CA US for advanced micro devices, inc.
IPC Code(s): G06F7/499, G06F7/02
CPC Code(s): G06F7/49984
Abstract: the disclosed circuit is configured to round a value in a first number format using a random value. using the rounded value, the circuit can convert the rounded value to a second number format that has a lower precision than a precision of the first number format. various other methods, systems, and computer-readable media are also disclosed.
20250130774. FLOATING POINT BIAS SWITCHING_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Shubh Shah of Santa Clara CA US for advanced micro devices, inc., Ashutosh Garg of Folsom CA US for advanced micro devices, inc., Bin He of Orlando FL US for advanced micro devices, inc., Michael Mantor of Orlando FL US for advanced micro devices, inc., Shubra Marwaha of Santa Clara CA US for advanced micro devices, inc., Subramaniam Maiyuran of Folsom CA US for advanced micro devices, inc.
IPC Code(s): G06F7/556, G06F7/483
CPC Code(s): G06F7/556
Abstract: the disclosed circuit can interpret a bit sequence as a value based on one of multiple floating point number formats in a bias mode indicated by a bias mode indicator. the circuit can and perform an operation using the value in the bias mode. various other methods, systems, and computer-readable media are also disclosed.
20250130794. MULTI-FORMAT OPERAND CIRCUIT_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Shubh Shah of Santa Clara CA US for advanced micro devices, inc., Ashutosh Garg of Folsom CA US for advanced micro devices, inc., Bin He of Orlando FL US for advanced micro devices, inc., Michael Mantor of Orlando FL US for advanced micro devices, inc., Shubra Marwaha of Santa Clara CA US for advanced micro devices, inc., Subramaniam Maiyuran of Folsom CA US for advanced micro devices, inc.
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30007
Abstract: the disclosed processing circuit can perform an operation with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output result. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): Sean Keely of Austin TX US for advanced micro devices, inc., Kellie Marks of Sydney AU for advanced micro devices, inc.
IPC Code(s): G06F9/38, G06F15/80
CPC Code(s): G06F9/3856
Abstract: an apparatus and method for efficiently migrating the execution of threads between multiple parallel lanes of execution. in various implementations, a computing system includes multiple vector processing circuits of a compute circuit that executes multiple lanes of multiple waves. each lane includes a key indicating a path of execution. when a lane of the multiple lanes of execution executes a stream wave coalescing (swc) reorder instruction, a control circuit compares keys of waves that have previously executed the swc reorder instruction. when the number of lanes with a matching key exceeds a threshold and after identifying at least this number of lanes to swap, the control circuit swaps continuation state information (live active state information) between lanes of an emitting wave that do not have a matching key and lanes of contributing waves that do have a matching key. the resulting (reordered) emitting wave executes more efficiently, which increases performance.
Inventor(s): Reshma Lal of Vancouver WA US for advanced micro devices, inc., David A. Kaplan of Austin TX US for advanced micro devices, inc., Jelena Ilic of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06F9/455
CPC Code(s): G06F9/45558
Abstract: a security framework for virtual machines is described. in one or more implementations, a hardware platform comprises physical computer hardware, the physical computer hardware including one or more processing units and one or more memories. the system also includes a virtual machine monitor configured to virtualize the physical computer hardware of the hardware platform to instantiate a plurality of framework-secure virtual machines. further, the system includes a root framework-secure virtual machine instantiated by the virtual machine monitor. in accordance with the described techniques, the root framework-secure virtual machine is configured to control access to the hardware platform by the framework-secure virtual machines instantiated by the virtual machine monitor.
Inventor(s): James R. Magro of Lakeway TX US for advanced micro devices, inc., Kedarnath Balakrishnan of Bangalore IN for advanced micro devices, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/023
Abstract: a memory controller includes a command queue stage, an arbitration stage, and a dispatch queue. the command queue stage stores decoded memory access requests. the arbitration stage is operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, using a shred resource. the dispatch queue has first and second upstream ports for receiving the first and second memory commands, and a downstream port for conducting first data of the first memory commands time-multiplexed with second data of the second memory commands.
Inventor(s): Reshma Lal of Vancouver WA US for advanced micro devices, inc., David A. Kaplan of Austin TX US for advanced micro devices, inc., Jelena Ilic of Austin TX US for advanced micro devices, inc.
IPC Code(s): G06F12/14, G06F12/1009
CPC Code(s): G06F12/1475
Abstract: root-trusted guest memory page management is described. a root-trusted guest is loaded by a hardware platform and authenticated. the root-trusted guest is configured to manage memory operations of different guests via special privileges that permit the root-trusted guest to execute memory operations using a guest's private memory page. to do so, a guest page table includes a novel “t-bit” in each entry, which indicates whether the root-trusted guest or a different guest owns the associated memory page. each entry in the guest page table for the root-trusted guest additionally includes a “c-bit” that indicates whether the corresponding memory page is a protected page. combined c-bit and t-bit values for a page table entry dictate whether operations performed as part of handling a guest's memory request are offloaded from the hardware platform to the root-trusted guest.
20250131639. Dense Geometry Format_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Joshua David Barczak of Forest Hill MD US for advanced micro devices, inc., Mohammed Ahmed Muneam Al-Obaidi of St. Albans GB for advanced micro devices, inc., David Kirk McAllister of Holladay UT US for advanced micro devices, inc., Trevor James Hedstrom of San Diego CA US for advanced micro devices, inc.
IPC Code(s): G06T15/06, G06T17/10, G06T17/20
CPC Code(s): G06T15/06
Abstract: systems and methods described herein for storing primitive data for ray tracing and/or rasterization. the data is encoded efficiently into arrays of fixed-size data blocks using a data format which can be directly consumed for ray traversal or rasterization. vertex data in a block is pre-quantized and stored using a fixed-bit quantization grid. mesh connectivity is encoded using a triangle strips based on control values representing triangle interconnectivity, and a compressed index buffer storing indices for vertices in each strip. further, triangle identifiers are derived from the triangle's position in the strip. the block can further store geometry identifiers and opacity maps corresponding to primitive data.
Inventor(s): Joshua David Barczak of Forest Hill MD US for advanced micro devices, inc., Mohammed Ahmed Muneam Al-Obaidi of St. Albans GB for advanced micro devices, inc., David Kirk McAllister of Holladay UT US for advanced micro devices, inc., Andrew Erin Kensler of Seattle WA US for advanced micro devices, inc.
IPC Code(s): G06T15/06
CPC Code(s): G06T15/06
Abstract: systems and methods for ray intersection against primitives are described. primitive data is encoded efficiently into arrays of fixed-size data blocks using a data format which can be directly consumed for ray traversal. vertex data in a block is pre-quantized and stored using a fixed-bit quantization grid. mesh connectivity is encoded using a triangle strips based on control values representing triangle interconnectivity, and a compressed index buffer storing indices for vertices in each strip. primitives can alternatively be quantized to generate primitive packets, that are stored compactly in, with, or near a leaf node of an acceleration structure. low-precision intersection testers test a ray simultaneously against primitives to find candidate triangles that require full-precision intersection. primitives that generate an inconclusive result during low-precision testing are retested using full-precision testers to definitively determine ray-triangle hits or misses.
Inventor(s): David Kirk McAllister of Holladay UT US for advanced micro devices, inc., Joshua David Barczak of Forest Hill MD US for advanced micro devices, inc., Andrew Erin Kensler of Seattle WA US for advanced micro devices, inc.
IPC Code(s): G06T15/06, G06T1/20, G06T1/60
CPC Code(s): G06T15/06
Abstract: systems and methods described herein for encoding geometrical primitives into data blocks are disclosed. in an implementation, these data blocks can be directly consumed by an application programming interface (api) for ray traversal or rasterization. a graphics application running on a ray tracing system provides primitive data to the graphics api using a data format that defines fixed-point, compressed, and fixed-size data blocks to store encoded primitive data. the stored data can be decompressed to construct an acceleration structure. data from the graphics application undergoes geometry clustering in a manner that these can be directly exposed by the api to be consumed by a processing circuitry when constructing acceleration structures.
20250132270. CHIP PACKAGE WITH TAMPER PREVENTION_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Mohit ARORA of Austin TX US for advanced micro devices, inc., Deepak Vasant KULKARNI of Austin TX US for advanced micro devices, inc., Richard E. GEORGE of Santa Clara CA US for advanced micro devices, inc., Terry Eugene RICHARDSON of Austin TX US for advanced micro devices, inc.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065
CPC Code(s): H01L23/576
Abstract: a chip package includes a package substrate and an integrated circuit (ic) die disposed on the package substrate. the ic dies includes a security asset. the chip package also includes a glass based shield selectively disposed on the ic die and above the security asset. the glass based shield is configured to block access to the security asset. in some embodiments, the chip package includes an oxide layer disposed between the glass based shield and the ic die. in some embodiments, the chip package includes a detection module and a wire connecting the detection module to the glass based shield. the detection module is configured to generate and send a serial bit stream to the glass based shield. the detection module is also configured to monitor for changes in the serial bit stream returning from the glass based shield. changes detected in the serial bit stream indicates the glass based shield has been tampered.
Inventor(s): Raghava SIVARAMU of Santa Clara CA US for advanced micro devices, inc., Vipin JAIN of Santa Clara CA US for advanced micro devices, inc., Rajshekhar BIRADAR of Bangalore IN for advanced micro devices, inc.
IPC Code(s): H04L67/1097
CPC Code(s): H04L67/1097
Abstract: embodiments herein describe creating multiple packet fragments from a large data chunk that, for example, exceeds a maximum transmission unit (mtu) supported by a network. in one embodiment, a network interface controller or card (nic) receives a direct memory access (dma) from a connected host to transmit an ip packet or data using remote direct memory access (rdma) technologies. the nic can evaluate the data chunk associated with the dma request and determine whether it exceeds the mtu for the network. assuming it does, the nic determines how many fragments to divide the data chunk into, and can fragment any portion of the data at flexible packet/payload offsets. the nic can then retrieve the data chunk from host memory fragment-by-fragment, rather than reading the data chunk all at once, generating headers for the fragments, and then transmit them as packet fragments.
Advanced Micro Devices, Inc. patent applications on April 24th, 2025
- Advanced Micro Devices, Inc.
- G06F3/06
- CPC G06F3/0611
- Advanced micro devices, inc.
- G06F7/483
- CPC G06F7/483
- G06F7/499
- G06F7/02
- CPC G06F7/49984
- G06F7/556
- CPC G06F7/556
- G06F9/30
- CPC G06F9/30007
- G06F9/38
- G06F15/80
- CPC G06F9/3856
- G06F9/455
- CPC G06F9/45558
- G06F12/02
- CPC G06F12/023
- G06F12/14
- G06F12/1009
- CPC G06F12/1475
- G06T15/06
- G06T17/10
- G06T17/20
- CPC G06T15/06
- G06T1/20
- G06T1/60
- H01L23/00
- H01L25/00
- H01L25/065
- CPC H01L23/576
- H04L67/1097
- CPC H04L67/1097
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