INTEGRATED CIRCUIT DEVICE

Abstract: an integrated circuit device includes a substrate, a fin-type active area on the substrate, a nanosheet stacked structure including a plurality of nanosheets, a gate electrode surrounding the nanosheet stacked structure on the fin-type active area, and a source/drain region connected to one end of the plurality of nanosheets on the fin-type active area, wherein the source/drain region includes a first source/drain layer in contact with the upper surface of the fin-type active area and side surfaces of the plurality of nanosheets, a second source/drain layer covering the first source/drain layer, a third source/drain layer covering part of the second source/drain layer, and a fourth source/drain layer covering the second source/drain layer and the third source/drain layer.

Inventor(s): Sumin Yu, Jungtaek Kim, Moonseung Yang, Yonguk Jeon, Edward Namkyu Cho, Seokhoon Kim, Pankwi Park

CPC Classification: H10D30/502 (No explanation available)

Search for rejections for patent application number 20250234580