THREE-STATE BUFFER CIRCUIT

Abstract: presented herein is a three-state buffer circuit having a voltage follower for directly driving a sampling capacitor at an output terminal of the three-state buffer circuit. the three-state buffer circuit further includes a switched capacitor circuit connected at an input of the voltage follower and configured to control the voltage follower to operate in one of a plurality of states. the states are: a tracking state, at which the voltage follower is configured to provide an output voltage at the output terminal at a level corresponding to an input voltage at an input terminal of the three-state buffer circuit; a hold state, at which the voltage follower is configured not to provide any output voltage at the output terminal; and a reset state at which the voltage follower is configured to provide an output voltage at the output terminal at a reset voltage.

Inventor(s): Nikola IVANISEVIC, Daniele MASTANTUONO, Mattias PALM

CPC Classification: H03M1/124 ({Sampling or signal conditioning arrangements specially adapted for A/D converters})

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