20250233070. Stacked Transistors Vertical Interconn (Taiwan Semiconductor Manufacturing , .)

STACKED TRANSISTORS WITH VERTICAL INTERCONNECT

Abstract: in an embodiment, a semiconductor device may include a plurality of first nanostructures. the plurality of first nanostructures extend between first source/drain regions. the semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. the plurality of second nanostructures extend between second source/drain regions. the device may furthermore include a first gate stack around the plurality of first nanostructures. the device may in addition include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. the device may moreover include a vertical interconnect structure extending through the first and second gate stacks. the device may also include a frontside contact electrically coupled to a frontside of the vertical interconnect structure and a backside contact electrically coupled to a backside of the vertical interconnect structure.

Inventor(s): Shao-Tse Huang, Jin-Hao Jhang, Wei-De Ho

CPC Classification: H01L23/5283 ({Geometry or} layout of the interconnection structure {( takes precedence; algorithms )})

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