STORING BITS WITH CELLS IN A MEMORY DEVICE

Abstract: methods, systems, and devices for storing bits, such as n−1 bits, with cells, such as n cells, in a memory device are described. a memory device may generate a first sensing voltage that is based on a first voltage of a first digit line and a second voltage of a second digit line. the memory device may also generate a second sensing voltage that is based on a third voltage of a third digit line and a fourth voltage of a fourth digit line. the memory device may then determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.

Inventor(s): Daniele Vimercati

CPC Classification: G11C16/26 (Sensing or reading circuits; Data output circuits)

Search for rejections for patent application number 20250232819