UNIFORM GIDL CURRENT DURING NAND ERASE

Abstract: technology for gate induced drain leakage (gidl) erase of nand strings. the drain-to-gate voltage of a source side select transistor (or transistors) is trimmed to compensate for different physical characteristics of the nand strings in different regions of a memory system. the drain-to-gate voltage generates a gidl current at the source end of a nand string during a gidl erase. the memory system uses different magnitudes for the drain-to-gate voltage applied to source side select transistor(s) on nand strings in different regions of the memory system to provide for more uniform gidl current during erase.

Inventor(s): Jiahui Yuan, Sarath Puthenthermadam, Abu Naser Zainuddin

CPC Classification: G11C16/16 (STATIC STORES (semiconductor memory devices ))

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