MEMORY DEVICE AND OPERATING METHOD THEREOF

Abstract: a memory device includes a first memory cell including channel, source and drain structures and a charge trap layer. when a first data bit has a first logic value and a voltage signal applied to the charge trap layer has a first voltage level, a current signal flowing through the channel structure has a first current level. when the first data bit has the first logic value and the voltage signal has a second voltage level, the current signal has a second current level. when the first data bit has a second logic value and the voltage signal has the first voltage level, the current signal has the second current level. when the first data bit has the second logic value and the voltage signal has the second voltage level, the current signal has the first current level.

Inventor(s): Po-Hao TSENG, Feng-Min LEE

CPC Classification: G11C15/046 (STATIC STORES (semiconductor memory devices ))

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