MEMORY SYSTEM AND MEMORY DEVICE

Abstract: according to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. the controller is configured to write a first portion of each of first data to n-th data from among n�j data with consecutive logical addresses to the n memory cells one by one. the first data has a lowest logical address among the n�j pieces of data. the first data to the n-th data have ascending consecutive logical addresses. the controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

Inventor(s): Naomi TAKEDA, Masanobu SHIRAKAWA, Akio SUGAHARA

CPC Classification: G11C11/5628 ({Programming or writing circuits; Data input circuits})

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