DRIVER AND DISPLAY DEVICE

Abstract: at least one stage of a driver includes an input circuit transferring an input signal to a first node in response to at least one of a clock signal and an inverted clock signal, a holding capacitor holding a voltage of the first node, a first inverter generating a voltage of a second node by inverting the voltage of the first node, a second inverter generating a voltage of a third node by inverting the voltage of the second node, a third inverter generating a carry signal by inverting the voltage of the second node, and an output control circuit selectively outputting the voltage of the third node as an output signal in response to an output enable signal. at least one of the first, second, third inverters, and the output control circuit includes a pmos transistor and an nmos transistor that are connected in series.

Inventor(s): SOON-DONG KIM, TAEHOON KIM

CPC Classification: G09G3/3275 (Details of drivers for data electrodes)

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