LOW LATENCY MATRIX MULTIPLY UNIT

Abstract: methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. each cell of the matrix multiply includes: a weight matrix register configured to receive a weight input from either a transposed or a non-transposed weight shift register; a transposed weight shift register configured to receive a weight input from a horizontal direction to be stored in the weight matrix register; a non-transposed weight shift register configured to receive a weight input from a vertical direction to be stored in the weight matrix register; and a multiply unit that is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.

Inventor(s): Andrew Everett Phelps, Norman Paul Jouppi

CPC Classification: G06F17/16 (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition )})

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