PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQUESTS

Abstract: devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. a barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.

Inventor(s): Christopher Baronne

CPC Classification: G06F12/126 (Replacement control)

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