LARGE INTEGER MULTIPLICATION ENHANCEMENTS FOR GRAPHICS ENVIRONMENT

Abstract: an apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. the apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (mad) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the mad instruction to generate an output in a single clock cycle of the processor.

Inventor(s): Supratim Pal, Li-An Tang, Changwon Rhee, Timothy R. Bauer, Alexander Lyashevsky, Jiasheng Chen

CPC Classification: G06F9/3001 ({Arithmetic instructions})

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