Display with Gate Driver Circuitry Controlled by True and Complementary Clock Signals

Abstract: a display may include an array of pixels that receive row control signals from gate driver circuitry. the gate driver circuitry can include a chain of gate drivers configured to receive one or more clock signals. the gate driver circuitry can further include inverters configured to invert the one or more clock signals to generate inverted clock signals. the clock signals and the inverted clock signals can be conveyed to the chain of gate drivers. falling edges of the clock signals and the inverted clock signals can be used to trigger assertions and deassertions of the row control signals. operated in this way, the power consumption of the gate driver circuitry can be reduced.

Inventor(s): Gihoon Choo, Tsung-Ting Tsai, Shyuan Yang, Abbas Jamshidi Roudbari, Chin-Wei Lin, Mao-Hsun Cheng, Salman Kabir, Ting-Kuo Chang, Warren S. Rieutort-Louis, Yuchi Che, Qing Li, Cheng-Chih Hsieh

CPC Classification: G06F1/10 (Distribution of clock signals {, e.g. skew})

Search for rejections for patent application number 20250231580