DEVICE INCLUDING STRUCTURE FOR PROTECTING ELEMENTS IN POWER DOWN MODE

Abstract: a device includes: a plurality of first transistors included in a first current path, in a normal mode, between a first power node to which a positive supply voltage is configured to be applied and a second power node to which a negative supply voltage is configured to be applied; and a first protection transistor connected to a first node which two of the plurality of first transistors are connected to, wherein the first protection transistor is configured to be turned off in the normal mode and to be turned on to provide a protection voltage to the first node in a power down mode.

Inventor(s): Himchan PARK, Jooseong Kim, Junhyeok Yang, Sungmin Yoo, Haejung Choi

CPC Classification: H10D89/811 (No explanation available)

Search for rejections for patent application number 20250221056