20250221041. Integrated Circuit Structure (Intel)
INTEGRATED CIRCUIT STRUCTURE WITH FRONT-SIDE-GUIDED BACKSIDE SOURCE OR DRAIN CONTACT
Abstract: integrated circuit structures having front-side-guided backside source or drain contacts are described. in an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. a first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. a second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. a dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.
Inventor(s): Leonard P. GULER, Jessica PANELLA, Vivek VISHWAKARMA, Kalpesh MAHAJAN, Dincer UNLUER, Umang DESAI, Ehren MANNEBACH, Sean PURSEL, Shaun MILLS, Joseph D’SILVA
CPC Classification: H10D86/60 (No explanation available)
Search for rejections for patent application number 20250221041
- Patent Applications
- Intel Corporation
- CPC H10D86/60
- Leonard P. GULER of Hillsboro OR US
- Jessica PANELLA of Banks OR US
- Vivek VISHWAKARMA of Vancouver WA US
- Kalpesh MAHAJAN of Portland OR US
- Dincer UNLUER of Hillsboro OR US
- Umang DESAI of Portland OR US
- Ehren MANNEBACH of Beaverton OR US
- Sean PURSEL of Tigard OR US
- Shaun MILLS of Hillsboro OR US
- Joseph D’SILVA of Hillsboro OR US