20250221019. Integrated Circuit Structure (Intel)
INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TRENCH CONTACT PLUG WITH GATE VOLTAGE THRESHOLD (VT) ADJUSTMENT
Abstract: integrated circuit structures having uniform grid metal gate and trench contact cut are described. for example, an integrated circuit structure includes a first and second vertical stacks of horizontal nanowires or fins. a first gate structure is over the first vertical stack of horizontal nanowires or fin, and a second gate structure is over the second vertical stack of horizontal nanowires or fin, the second gate structure having voltage threshold (vt) different than a vt of the first gate structure. a conductive trench contact is adjacent to the first gate structure and the second gate structure. a dielectric sidewall spacer is between the first gate structure and the conductive trench contact, and between the second gate structure and the conductive trench contact. a dielectric cut plug structure is extending between the first gate structure and the second gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.
Inventor(s): Leonard P. GULER, Dan S. LAVRIC, Hongqian SUN, Vivek VISHWAKARMA, Shengsi LIU, Marvin Y. PAIK, Gianna DI FRANCESCO, Gabriela DILLIWAY, Suman DASGUPTA, Dimitri KIOUSSIS
CPC Classification: H10D84/83 (No explanation available)
Search for rejections for patent application number 20250221019
- Patent Applications
- Intel Corporation
- CPC H10D84/83
- Leonard P. GULER of Hillsboro OR US
- Dan S. LAVRIC of Portland OR US
- Hongqian SUN of Sammamish WA US
- Vivek VISHWAKARMA of Vancouver WA US
- Shengsi LIU of Portland OR US
- Marvin Y. PAIK of Portland OR US
- Gianna DI FRANCESCO of Portland OR US
- Gabriela DILLIWAY of Beaverton OR US
- Suman DASGUPTA of San Diego CA US
- Dimitri KIOUSSIS of San Jose CA US