INTEGRATED CIRCUIT STRUCTURE WITH ASYMMETRIC EPITAXIAL SOURCE OR DRAIN ARRANGEMENTS

Abstract: integrated circuit structures having asymmetric epitaxial source or drain arrangements are described. an integrated circuit structure includes a gate stack over a plurality of horizontally stacked nanowires. a first epitaxial source or drain structure is at a first end of the plurality of horizontally stacked nanowires. a first gate spacer laterally between the gate stack and the first epitaxial source or drain structure. a second epitaxial source or drain structure is at a second end of the plurality of horizontally stacked nanowires. a second gate spacer is laterally between the gate stack and the first epitaxial source or drain structure. the first gate spacer has a width less than the second gate spacer or the tips of the first epitaxial source or drain structure have a greater lateral width than the tips of the second epitaxial source or drain structure by an amount of 10% or greater, or both.

Inventor(s): Gilbert DEWEY, Ehren MANNEBACH, Shaun MILLS, Valur GUDMUNDSSON, Joseph D’SILVA, Mauro J. KOBRINSKY, Makram ABD EL QADER, Debaleena NANDI

CPC Classification: H10D30/6757 (No explanation available)

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