VERTICALLY STACKED MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME

Abstract: a memory device includes a bit line extending in a first direction, an oxide semiconductor layer extending in a second direction intersecting the first direction and connected to the bit line, the oxide semiconductor layer comprising a source region, a drain region, and a channel region between the source region and the drain region, a capacitor electrically connected to the oxide semiconductor layer, a word line extending to intersect the oxide semiconductor layer in a third direction intersecting the first direction and the second direction, a first insulator on both side surfaces of the source region and the drain region in the third direction, and a second insulator different from the first insulator and on both sides of the channel region in the third direction.

Inventor(s): Sangwook KIM, Younjin JANG, Moonil JUNG, Narae HAN

CPC Classification: H10B12/488 (ELECTRONIC MEMORY DEVICES)

Search for rejections for patent application number 20250220892