SEMICONDUCTOR DEVICE AND STACK OF SEMICONDUCTOR CHIPS

Abstract: a semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

Inventor(s): Shaofeng DING, Jeong Hoon AHN, Yun Ki CHOI

CPC Classification: H10B10/18 (ELECTRONIC MEMORY DEVICES)

Search for rejections for patent application number 20250220874