SYSTEMS AND METHODS FOR USING PROGRAMMABLE POLICER CIRCUITS FOR NETWORK FLOW POLICING

Abstract: the packet processing chip of a networking device includes a packet processing pipeline circuit and a programmable policer circuit. a single programmable policer circuit may use policing policy identifiers and an aggregated token bucket to police multiple network flows. a policing policy identifier may govern which policing policy is used for a network packet. each network flow may have a flow table entry that includes a policing policy identifier and a programmable policer circuit identifier. after reading the flow table entry for processing a network packet, the packet processing pipeline circuit may send data including the policing policy identifier to the programmable policer circuit which returns a policing decision in accordance with the policing policy and the state of the aggregated token bucket. different network flows may use the same aggregated token buck and different policing policies to thereby implement strict priority of some network flows over others.

Inventor(s): Vishwas Danivas, Kit Chiu Chu, Murty Kotha

CPC Classification: H04L47/20 (Traffic policing)

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