ENCRYPTION/DECRYPTION DEVICE WITH VERIFICATION MECHANISM

Abstract: an encryption and decryption device includes a shiftrow/invshiftrow unit, a subbytes/invsubbytes unit, a dual shiftrow/invshiftrow unit, an encoder, a decoder, and a first verification unit. the shiftrow/invshiftrow unit performs a row shift/inverse row shift operation on result data to generate an input state array. the subbytes/invsubbytes unit performs a transformation on the input state array to generate an output state array. the dual shiftrow/invshiftrow unit performs the row shift/inverse row shift operation on dual output data to generate a dual input state array. the encoder encodes the dual input state to generate encoded data. the decoder decodes the encoded data to generate decoded data. the first verification unit verifies the mapping relationship of the decoded data and the output state array to generate a first verification signal.

Inventor(s): Kun-Yi WU, Yu-Shan LI

CPC Classification: H04L9/0631 ({Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms})

Search for rejections for patent application number 20250219809