CROSS-COUPLED TIMING SYNCHRONIZATION PLATFORM

Abstract: apparatuses, devices, and systems for time synchronization are described. a timing circuit can include an analog phase lock loop (apll), a plurality of digital phase lock loops (dplls) and a plurality of fractional output dividers (fods). the timing circuit can receive the plurality of reference clock signals. the timing circuit can use the plurality of reference clock signals to generate at least one fractional frequency offset signal. the timing circuit can apply at least one operand on the at least one fractional frequency offset signal. the timing circuit can sum results of the application of the at least one operand on the at least one fractional frequency offset signal to generate a plurality of signals that control frequencies of a plurality of output clock signals that can be synchronized with the plurality of reference clock signals.

Inventor(s): Menno SPIJKER, Michael RUPERT, Veronique ALLARD, Ketsana SOUKSANH

CPC Classification: H03L7/1976 ({using a phase accumulator for controlling the counter or frequency divider})

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